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Groups > linux.kernel > #1632281
| From | Will Deacon <will.deacon@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 |
| Date | 2017-04-27 19:40 +0200 |
| Message-ID | <tAVyy-3KJ-27@gated-at.bofh.it> (permalink) |
| References | <typCO-4oW-11@gated-at.bofh.it> <typCO-4oW-23@gated-at.bofh.it> <tA84O-4Mb-15@gated-at.bofh.it> <tAci5-7A0-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Tue, Apr 25, 2017 at 10:13:51AM -0700, Florian Fainelli wrote: > On 04/25/2017 05:44 AM, Will Deacon wrote: > > Hi Florian, > > > > On Thu, Apr 20, 2017 at 12:05:46PM -0700, Florian Fainelli wrote: > >> The ARMv8 PMUv3 cache map did not include the L2 cache events, add > >> them. > >> > >> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > >> --- > >> arch/arm64/kernel/perf_event.c | 5 +++++ > >> 1 file changed, 5 insertions(+) > >> > >> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > >> index 4f011cdd756d..a664c575f3fd 100644 > >> --- a/arch/arm64/kernel/perf_event.c > >> +++ b/arch/arm64/kernel/perf_event.c > >> @@ -264,6 +264,11 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] > >> [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, > >> [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, > >> > >> + [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE, > >> + [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL, > >> + [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE, > >> + [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL, > > > > I don't think this is correct in general. 'LL' stands for "last-level", > > which may be L3 or even a system cache in the interconnect. Tying that to L2 > > is the wrong thing to do from perf's generic event perspective. > > > > I'm ok with what you're proposing for A53 (where the PMU can only count > > events out to the L2), but I'm reluctant to make this change for the generic > > PMUv3 events. > > That makes sense, shall I resubmit the first patch by itself or can you > or Catalin take it as-is? I'll talk to Catalin tomorrow and try to get the A53 bit queued. Will
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Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Will Deacon <will.deacon@arm.com> - 2017-04-25 14:50 +0200
Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Florian Fainelli <f.fainelli@gmail.com> - 2017-04-25 19:20 +0200
Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Will Deacon <will.deacon@arm.com> - 2017-04-27 19:40 +0200
Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Catalin Marinas <catalin.marinas@arm.com> - 2017-04-28 16:20 +0200
Re: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Will Deacon <will.deacon@arm.com> - 2017-04-28 16:20 +0200
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