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[PATCH 1/4] Documentation: bindings: add uphy-dp-sel for Rockchip USB Type-C PHY

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rockchip,uphy-dp-sel is the register of type-c phy enable DP function.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
index 6ea867e..c3be83b 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
@@ -33,6 +33,9 @@ offset, enable bit, write mask bit.
  - rockchip,pipe-status : the register of type-c phy pipe status.
    for type-c phy0, it must be <0xe5c0 0 0>;
    for type-c phy1, it must be <0xe5c0 16 16>;
+ - rockchip,uphy-dp-sel : the register of type-c phy enable DP function
+   for type-c phy0, it must be <0x6268 19 19>;
+   for type-c phy1, it must be <0x6268 3 19>;
 
 Required nodes : a sub-node is required for each port the phy provides.
 		 The sub-node name is used to identify dp or usb3 port,
@@ -62,6 +65,7 @@ Example:
 		rockchip,usb3tousb2-en = <0xe580 3 19>;
 		rockchip,external-psm = <0xe588 14 30>;
 		rockchip,pipe-status = <0xe5c0 0 0>;
+		rockchip,uphy-dp-sel = <0x6268 19 19>;
 
 		tcphy0_dp: dp-port {
 			#phy-cells = <0>;
@@ -90,6 +94,7 @@ Example:
 		rockchip,usb3tousb2-en = <0xe58c 3 19>;
 		rockchip,external-psm = <0xe594 14 30>;
 		rockchip,pipe-status = <0xe5c0 16 16>;
+		rockchip,uphy-dp-sel = <0x6268 3 19>;
 
 		tcphy1_dp: dp-port {
 			#phy-cells = <0>;
-- 
2.6.3

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[PATCH 0/4] Move DP phy switch to PHY driver Chris Zhong <zyw@rock-chips.com> - 2017-02-10 09:00 +0100
  [PATCH 1/4] Documentation: bindings: add uphy-dp-sel for Rockchip USB Type-C PHY Chris Zhong <zyw@rock-chips.com> - 2017-02-10 09:00 +0100
  [PATCH 3/4] phy: rockchip-typec: support DP phy switch Chris Zhong <zyw@rock-chips.com> - 2017-02-10 09:00 +0100
  [PATCH 2/4] arm64: dts: rockchip: add rockchip,uphy-dp-sel for Type-C phy Chris Zhong <zyw@rock-chips.com> - 2017-02-10 10:00 +0100

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