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Groups > linux.kernel > #1573873
| From | tip-bot for Yazen Ghannam <tipbot@zytor.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [tip:x86/urgent] x86/CPU/AMD: Fix Zen SMT topology |
| Date | 2017-02-05 12:40 +0100 |
| Message-ID | <t7tkJ-6Hi-5@gated-at.bofh.it> (permalink) |
| References | <t7sI2-6dH-15@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Commit-ID: 08b259631b5a1d912af4832847b5642f377d9101
Gitweb: http://git.kernel.org/tip/08b259631b5a1d912af4832847b5642f377d9101
Author: Yazen Ghannam <Yazen.Ghannam@amd.com>
AuthorDate: Sun, 5 Feb 2017 11:50:22 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Sun, 5 Feb 2017 12:18:45 +0100
x86/CPU/AMD: Fix Zen SMT topology
After:
a33d331761bc ("x86/CPU/AMD: Fix Bulldozer topology")
our SMT scheduling topology for Fam17h systems is broken, because
the ThreadId is included in the ApicId when SMT is enabled.
So, without further decoding cpu_core_id is unique for each thread
rather than the same for threads on the same core. This didn't affect
systems with SMT disabled. Make cpu_core_id be what it is defined to be.
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@vger.kernel.org> # 4.9
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20170205105022.8705-2-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/amd.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 20dc44d..2b4cf04 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -319,6 +319,13 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
if (c->x86 == 0x15)
c->cu_id = ebx & 0xff;
+ if (c->x86 >= 0x17) {
+ c->cpu_core_id = ebx & 0xff;
+
+ if (smp_num_siblings > 1)
+ c->x86_max_cores /= smp_num_siblings;
+ }
+
/*
* We may have multiple LLCs if L3 caches exist, so check if we
* have an L3 cache by looking at the L3 cache CPUID leaf.
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[PATCH 1/2] x86/CPU/AMD: Bring back Compute Unit ID Borislav Petkov <bp@alien8.de> - 2017-02-05 12:00 +0100
[PATCH 2/2] x86/CPU/AMD: Fix Zen SMT topology Borislav Petkov <bp@alien8.de> - 2017-02-05 12:00 +0100
[tip:x86/urgent] x86/CPU/AMD: Fix Zen SMT topology tip-bot for Yazen Ghannam <tipbot@zytor.com> - 2017-02-05 12:40 +0100
[tip:x86/urgent] x86/CPU/AMD: Bring back Compute Unit ID tip-bot for Borislav Petkov <tipbot@zytor.com> - 2017-02-05 12:40 +0100
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