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Re: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration

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On Sun, Jan 29, 2017 at 01:24:37PM +0000, John Keeping wrote:
> The multiplication ratio for the PLL is required to be even due to the
> use of a "by 2 pre-scaler".  Currently we are likely to end up with an
> odd multiplier even though there is an equivalent set of parameters with
> an even multiplier.
> 
> For example, using the 324MHz bit rate with a reference clock of 24MHz
> we end up with M = 27, N = 2 whereas the example in the PHY databook
> gives M = 54, N = 4 for this bit rate and reference clock.
> 
> By walking down through the available multiplier instead of up we are
> more likely to hit an even multiplier.  With the above example we do now
> get M = 54, N = 4 as given by the databook.
> 
> While doing this, change the loop limits to encode the actual limits on
> the divisor, which are:
> 
> 	40MHz >= (pllref / N) >= 5MHz
> 
> Signed-off-by: John Keeping <john@metanate.com>
> ---
> Unchanged in v3
> Unchanged in v2
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 85edf6dd2bac..dcb66a21e1f1 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -522,7 +522,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
>  	pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
>  	tmp = pllref;
>  
> -	for (i = 1; i < 6; i++) {
> +	for (i = pllref / 5; i > (pllref / 40); i--) {

I've convinced myself that this is right, but it took reading through the commit
message a few times. I think this code would benefit greatly from a comment so
readers don't need to go through git history.

With that,

Reviewed-by: Sean Paul <seanpaul@chromium.org>


>  		pre = pllref / i;
>  		if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
>  			tmp = target_mbps % pre;
> -- 
> 2.11.0.197.gb556de5.dirty
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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Re: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL  configuration Sean Paul <seanpaul@chromium.org> - 2017-01-31 20:20 +0100

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