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[PATCH] x86/fpu/xstate: Move XSAVES state init to a function

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Make XSTATE init similar to existing code; move it to a separate function.
There is no functionality change.

Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
---
 arch/x86/include/asm/fpu/internal.h | 11 +++++++++++
 arch/x86/kernel/fpu/core.c          |  8 +-------
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/fpu/internal.h b/arch/x86/include/asm/fpu/internal.h
index d4a6849..7fed690 100644
--- a/arch/x86/include/asm/fpu/internal.h
+++ b/arch/x86/include/asm/fpu/internal.h
@@ -87,6 +87,17 @@ static __always_inline __pure bool use_fxsr(void)
 #else
 static inline void fpstate_init_soft(struct swregs_state *soft) {}
 #endif
+
+static inline void fpstate_init_xstate(struct xregs_state *xsave)
+{
+	/*
+	 * XRSTORS requires that these bits set in xcomp_bv, or it will
+	 * trigger #GP. Make sure they are replaced after memset().
+	 */
+	xsave->header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT |
+				 xfeatures_mask;
+}
+
 static inline void fpstate_init_fxstate(struct fxregs_state *fx)
 {
 	fx->cwd = 0x37f;
diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c
index de72344..5763b27 100644
--- a/arch/x86/kernel/fpu/core.c
+++ b/arch/x86/kernel/fpu/core.c
@@ -179,14 +179,8 @@ void fpstate_init(union fpregs_state *state)
 
 	memset(state, 0, fpu_kernel_xstate_size);
 
-	/*
-	 * XRSTORS requires that this bit is set in xcomp_bv, or
-	 * it will #GP. Make sure it is replaced after the memset().
-	 */
 	if (static_cpu_has(X86_FEATURE_XSAVES))
-		state->xsave.header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT |
-					       xfeatures_mask;
-
+		fpstate_init_xstate(&state->xsave);
 	if (static_cpu_has(X86_FEATURE_FXSR))
 		fpstate_init_fxstate(&state->fxsave);
 	else
-- 
1.9.1

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[PATCH] x86/fpu/xstate: Move XSAVES state init to a function Yu-cheng Yu <yu-cheng.yu@intel.com> - 2017-01-24 19:40 +0100
  [tip:x86/fpu] x86/fpu/xstate: Move XSAVES state init to a function tip-bot for Yu-cheng Yu <tipbot@zytor.com> - 2017-01-25 09:40 +0100

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