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Re: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum 161010801

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On Tue, Jan 24, 2017 at 01:47:57PM +0000, Shameerali Kolothum Thodi wrote:
> The HiSilicon erratum 161010801 describes the limitation of certain
> HiSilicon platforms to support the SMMU mappings for MSI transactions.
> 
> On these platforms GICv3 ITS translator is presented with the deviceID
> by extending the MSI payload data to 64 bits to include the deviceID.
> Hence, the PCIe controller on this platforms has to differentiate the
> MSI payload against other DMA payload and has to modify the MSI payload.
> This basically makes it difficult for this platforms to have a SMMU
> translation for MSI.

Do you mean that the PCIe root controller looking at the (virtual)
addresses of DMA and comparing these against the (physical) address of
the ITS in order to determine if a write is an MSI?

I can't see anything in this patch specifically enabling bypass for
MSIs. Do writes to the ITS (physical) address always bypass the SMMU,
and go straight to the ITS? Regardless of translation applied to other
DMA?

It sounds like this will have severe implications for virtualization.

> Also these platforms doesn't have a proper IIDR
> register to use the existing IIDR based quirk mechanism.

What exactly is wrong with the IIDR on these platforms? That sounds like
an erratum as of itself.

What precise value do reads of the IIDR return? Or do reads result in
other erroneous behaviour?

Thanks,
Mark.

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[RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> - 2017-01-24 15:00 +0100
  Re: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Mark Rutland <mark.rutland@arm.com> - 2017-01-24 15:20 +0100
    RE: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> - 2017-01-25 11:40 +0100
  Re: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Marc Zyngier <marc.zyngier@arm.com> - 2017-01-24 15:20 +0100
    Re: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Robin Murphy <robin.murphy@arm.com> - 2017-01-24 15:50 +0100
      Re: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Marc Zyngier <marc.zyngier@arm.com> - 2017-01-24 16:00 +0100
      RE: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> - 2017-01-24 16:50 +0100
        Re: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Marc Zyngier <marc.zyngier@arm.com> - 2017-01-24 17:00 +0100
          RE: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> - 2017-01-24 17:20 +0100
            Re: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Robin Murphy <robin.murphy@arm.com> - 2017-01-24 17:40 +0100
              RE: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> - 2017-01-24 17:50 +0100
            Re: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Marc Zyngier <marc.zyngier@arm.com> - 2017-01-24 17:40 +0100
              Re: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Robin Murphy <robin.murphy@arm.com> - 2017-01-24 17:50 +0100
                RE: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum  161010801 Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> - 2017-01-24 18:00 +0100

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