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Re: [PATCH] pinctrl: aspeed: g4: Fix mux configuration for GPIOs AA[4-7], AB[0-7]

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On Mon, Jan 23, 2017 at 6:27 AM, Andrew Jeffery <andrew@aj.id.au> wrote:

> Incorrect video output configuration bits were being tested on pins in
> GPIO banks AA and AB for the ROM{8,16} mux functions. The ROM{8,16}
> functions are the highest priority for the relevant pins and also the
> default function, so we require the relevant video output configuration
> be disabled to mux GPIO functionality. As the wrong bits were being
> tested a GPIO export would succeed but leave the pin in an unresponsive
> state (i.e. value updates were ignored).
>
> This misbehaviour was discovered as part of extending the GPIO
> controller's support to cover banks Y, Z, AA, AB and AC (AC in the case
> of the g5 SoC).
>
> Fixes: 6d329f14a75f ("pinctrl: aspeed-g4: Add mux configuration for all pins")
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

Patch applied.

Yours,
Linus Walleij

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[PATCH] pinctrl: aspeed: g4: Fix mux configuration for GPIOs AA[4-7], AB[0-7] Andrew Jeffery <andrew@aj.id.au> - 2017-01-23 06:30 +0100
  Re: [PATCH] pinctrl: aspeed: g4: Fix mux configuration for GPIOs  AA[4-7], AB[0-7] Linus Walleij <linus.walleij@linaro.org> - 2017-01-26 14:50 +0100

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