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Groups > linux.kernel > #1562325
| From | Florian Fainelli <florian.fainelli@broadcom.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 2/7] ARM: Add Broadcom Brahma-B15 readahead cache support |
| Date | 2017-01-19 01:30 +0100 |
| Message-ID | <t18M1-2Gh-3@gated-at.bofh.it> (permalink) |
| References | <t15br-o6-7@gated-at.bofh.it> <t15bs-o6-27@gated-at.bofh.it> <t17mW-1Gi-33@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 01/18/2017 02:56 PM, Russell King - ARM Linux wrote: > On Wed, Jan 18, 2017 at 12:29:21PM -0800, Florian Fainelli wrote: >> The readahead cache only intercepts reads, not writes, as such, some >> data can remain stale in any of its buffers, such that we need to flush >> it, which is an operation that needs to happen in a particular order: >> >> - disable the readahead cache >> - flush it >> - call the appropriate cache-v7.S function >> - re-enable > > I really do hope that the above explanation is wrong, because if that's > really how it's implemented, it's going to cause coherency problems. > > It's got to at least monitor writes, otherwise how do you guarantee > that the CPU doesn't see stale data? IOW: Yes, it does monitor writes, the explanation given here was wrong. Thanks! > > Consider this at the L2 memory-side interface (iow, downstream of the > point-of-coherency): > > CPU1 CPU2 Read-ahead buffer > read cache line C > reads cache line C and C+1 > writes cache line C+1 > read cache line C+1 > > What ensures that CPU2 sees the written out cache line from CPU1? -- Florian
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[PATCH 0/7] ARM: Broadcom Brahma-B15 readahead cache support Florian Fainelli <f.fainelli@gmail.com> - 2017-01-18 21:40 +0100
[PATCH 1/7] ARM: v7: allow setting different cache functions Florian Fainelli <f.fainelli@gmail.com> - 2017-01-18 21:40 +0100
[PATCH 8/8] ARM: smp: Remove CPU: shutdown notice Florian Fainelli <f.fainelli@gmail.com> - 2017-01-18 21:40 +0100
[PATCH 7/7] MAINTAINERS: Update brcmstb entries to cover B15 code Florian Fainelli <f.fainelli@gmail.com> - 2017-01-18 21:40 +0100
[PATCH 2/7] ARM: Add Broadcom Brahma-B15 readahead cache support Florian Fainelli <f.fainelli@gmail.com> - 2017-01-18 21:40 +0100
Re: [PATCH 2/7] ARM: Add Broadcom Brahma-B15 readahead cache support Russell King - ARM Linux <linux@armlinux.org.uk> - 2017-01-19 00:00 +0100
Re: [PATCH 2/7] ARM: Add Broadcom Brahma-B15 readahead cache support Florian Fainelli <florian.fainelli@broadcom.com> - 2017-01-19 01:30 +0100
[PATCH 4/7] ARM: B15: Add CPU hotplug awareness Florian Fainelli <f.fainelli@gmail.com> - 2017-01-18 21:40 +0100
[PATCH 3/7] ARM: Hook B15 readahead cache functions based on processor Florian Fainelli <f.fainelli@gmail.com> - 2017-01-18 21:40 +0100
[PATCH 5/7] ARM: B15: Add suspend/resume hooks Florian Fainelli <f.fainelli@gmail.com> - 2017-01-18 21:40 +0100
[PATCH 6/7] ARM: B15: Register reboot notifier for KEXEC Florian Fainelli <f.fainelli@gmail.com> - 2017-01-18 21:40 +0100
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