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[PATCH v8 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features

From Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Newsgroups linux.kernel
Subject [PATCH v8 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features
Date 2016-11-03 17:10 +0100
Message-ID <szsKu-664-49@gated-at.bofh.it> (permalink)
References <szrEP-5cN-17@gated-at.bofh.it>
Organization linux.* mail to news gateway

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Add Intel Xeon Phi x200 (KnightsLanding) CPU feature - ring 3 MONITOR/MWAIT.

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 92a8308..98414c5 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -100,7 +100,7 @@
 #define X86_FEATURE_XTOPOLOGY	( 3*32+22) /* cpu topology enum extensions */
 #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
 #define X86_FEATURE_NONSTOP_TSC	( 3*32+24) /* TSC does not stop in C states */
-/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
+#define X86_FEATURE_PHIR3MWAIT	( 3*32+25) /* Xeon Phi x200 ring 3 MONITOR/MWAIT */
 #define X86_FEATURE_EXTD_APICID	( 3*32+26) /* has extended APICID (8 bits) */
 #define X86_FEATURE_AMD_DCM     ( 3*32+27) /* multi-node processor */
 #define X86_FEATURE_APERFMPERF	( 3*32+28) /* APERFMPERF */
-- 
2.5.1

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[PATCH v8: 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-11-01 11:20 +0100
  Re: [PATCH v8: 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Borislav Petkov <bp@suse.de> - 2016-11-03 16:00 +0100
    [PATCH v8 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-11-03 17:10 +0100

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