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[PATCH 1/2] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag

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The X86_FEATURE_TSC_RELIABLE flag in Linux kernel implies both reliable
(at runtime) and trustable (at calibration). But reliable running and
trustable calibration are logically irrelevant. Per Thomas Gleixner's
suggestion we would like to split this flag into two separate flags:
X86_FEATURE_TSC_RELIABLE - running reliably
X86_FEATURE_TSC_KNOWN_FREQ - frequency is known (no calibration required)
These two flags allow Linux kernel to act differently based on
processor/SoC's capability, i.e. no watchdog on TSC if TSC is reliable,
and no calibration if TSC frequency is known.

Current Linux kernel already gurantees calibration is skipped for
processors that can report TSC frequency by CPUID or MSR. However, the
delayed calibration is still not skipped for these CPUID/MSR capable
processors. The new flag X86_FEATURE_TSC_KNOWN_FREQ added by this patch
will gurantee the delayed calibration is skipped.

Signed-off-by: Bin Gao <bin.gao@intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/kernel/tsc.c              | 6 +++---
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index a396292..7f6a5f8 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -106,6 +106,7 @@
 #define X86_FEATURE_APERFMPERF	( 3*32+28) /* APERFMPERF */
 #define X86_FEATURE_EAGER_FPU	( 3*32+29) /* "eagerfpu" Non lazy FPU restore */
 #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
+#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3	( 4*32+ 0) /* "pni" SSE-3 */
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 46b2f41..b4c82f8 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1283,10 +1283,10 @@ static int __init init_tsc_clocksource(void)
 		clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
 
 	/*
-	 * Trust the results of the earlier calibration on systems
-	 * exporting a reliable TSC.
+	 * When TSC frequency is known (generally got by MSR or CPUID), we skip
+	 * the refined calibration and directly register it as a clocksource.
 	 */
-	if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
+	if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
 		clocksource_register_khz(&clocksource_tsc, tsc_khz);
 		return 0;
 	}
-- 
1.9.1

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[PATCH 0/2] x86/tsc: split X86_FEATURE_TSC_RELIABLE into two Bin Gao <bin.gao@intel.com> - 2016-11-01 18:10 +0100
  [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs Bin Gao <bin.gao@intel.com> - 2016-11-01 18:10 +0100
    Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain  processors/SoCs Thomas Gleixner <tglx@linutronix.de> - 2016-11-09 22:30 +0100
      Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on  certain processors/SoCs Bin Gao <bin.gao@linux.intel.com> - 2016-11-11 00:20 +0100
        Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on  certain processors/SoCs Thomas Gleixner <tglx@linutronix.de> - 2016-11-11 00:30 +0100
          Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on  certain processors/SoCs Bin Gao <bin.gao@linux.intel.com> - 2016-11-11 01:10 +0100
            Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on  certain processors/SoCs Thomas Gleixner <tglx@linutronix.de> - 2016-11-11 01:10 +0100
  [PATCH 1/2] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Bin Gao <bin.gao@intel.com> - 2016-11-01 18:10 +0100
    Re: [PATCH 1/2] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Thomas Gleixner <tglx@linutronix.de> - 2016-11-09 22:20 +0100
      Re: Re: [PATCH 1/2] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Bin Gao <bin.gao@linux.intel.com> - 2016-11-10 23:50 +0100

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