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Re: [PATCH v6 00/10] Intel Cache Allocation Technology

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Gentlemen!

After more than two years of tinkering and real engineering, we finaly have
skinned the CAT!

That was the most amazing review journey I ever made as a maintainer. Just
a few statistics:

Design variants: 6

  6 different approaches for a user space interface. 3 of them have been
  actually implemented.

  Unfortunately the real interface discussion happened way after the first
  rounds of patches had been sent and reviewed. See below.

Patchsets:	21

  21 patch sets were posted. These can be split into two generations.

  Gen1	   	16   Oct 2014 - Dec 2015

  Gen2		5    Jul 2016 - Oct 2016

LKML-Mails:	1216

  That's the number of mails related to this project sent to LKML,
  according to my archive. About 1/3 of those mails are the postings of
  the patchsets alone.

  I cannot tell how many offlist mails have been sent around in total on
  this matter, but at least in my personal mail are close to hundred.

Beers: 	       Uncountable

  This applies to both the number of beers consumed and the number of beers
  owed.

I'm pretty happy with the final outcome of these patches and I want to say
thanks to everyone!

I know that I've been a pain in the neck for some of you due to my
pedantery about the details, but getting this wrong would have been a major
disaster. If I offended someone personally in course of the sometimes
heated discussions, then I offer my excuses.

Some lessons can be learned from this endeavour:

   1) Chip vendors should give access to the full documentation early

   2) Reviewers should never trust patch submitters, that they have read
      the documentation correctly and came to the right conclusions how to
      handle such a facility.

   3) User space interface discussions should be done upfront with a full
      explanation of the inner workings of such a facility and full
      documentation available.

Anything else is just the usual churn of patch submissions, which are
handled by the submitters with different effectiveness levels.

That said, all which needs to be done now is proper testing and a massive
exposure of the user space interface to fuzzers. I've implemented my share
of string parsers in the past and as careful as I was, there was always a
hole in them.

If any of the involved folks are at KS/LPC then I suggest we get together
at a bar during the week and drown the skinned CAT with the appropriate
beverages. The first round of drinks is my shout.

Thanks,

	tglx

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[PATCH v6 00/10] Intel Cache Allocation Technology "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-29 00:10 +0200
  [PATCH v6 07/10] x86/intel_rdt: Add tasks files "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-29 00:10 +0200
    [tip:x86/cache] x86/intel_rdt: Add tasks files tip-bot for Fenghua Yu <tipbot@zytor.com> - 2016-10-31 02:30 +0100
  [PATCH v6 10/10] MAINTAINERS: Add maintainer for Intel RDT resource allocation "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-29 00:10 +0200
    [tip:x86/cache] MAINTAINERS: Add maintainer for Intel RDT resource  allocation tip-bot for Fenghua Yu <tipbot@zytor.com> - 2016-10-31 02:30 +0100
  [PATCH v6 02/10] x86/intel_rdt: Build structures for each resource based on cache topology "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-29 00:10 +0200
    [tip:x86/cache] x86/intel_rdt: Build structures for each resource  based on cache topology tip-bot for Tony Luck <tipbot@zytor.com> - 2016-10-31 02:30 +0100
  [PATCH v6 09/10] x86/intel_rdt: Add scheduler hook "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-29 00:10 +0200
    [tip:x86/cache] x86/intel_rdt: Add scheduler hook tip-bot for Fenghua Yu <tipbot@zytor.com> - 2016-10-31 02:30 +0100
  [PATCH v6 01/10] Documentation, x86: Documentation for Intel resource allocation user interface "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-29 00:10 +0200
    [tip:x86/cache] Documentation, x86: Documentation for Intel  resource allocation user interface tip-bot for Fenghua Yu <tipbot@zytor.com> - 2016-10-31 02:30 +0100
  [PATCH v6 04/10] x86/intel_rdt: Add "info" files to resctrl file system "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-29 00:10 +0200
    [tip:x86/cache] x86/intel_rdt: Add "info" files to resctrl file  system tip-bot for Fenghua Yu <tipbot@zytor.com> - 2016-10-31 02:30 +0100
  [PATCH v6 03/10] x86/intel_rdt: Add basic resctrl filesystem support "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-29 00:10 +0200
    Re: [PATCH v6 03/10] x86/intel_rdt: Add basic resctrl filesystem  support Thomas Gleixner <tglx@linutronix.de> - 2016-10-31 02:20 +0100
    [tip:x86/cache] x86/intel_rdt: Add basic resctrl filesystem support tip-bot for Fenghua Yu <tipbot@zytor.com> - 2016-10-31 02:30 +0100
  [PATCH v6 05/10] x86/intel_rdt: Add mkdir to resctrl file system "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-29 00:10 +0200
    [tip:x86/cache] x86/intel_rdt: Add mkdir to resctrl file system tip-bot for Fenghua Yu <tipbot@zytor.com> - 2016-10-31 02:30 +0100
  [PATCH v6 06/10] x86/intel_rdt: Add cpus file "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-29 00:10 +0200
    [tip:x86/cache] x86/intel_rdt: Add cpus file tip-bot for Tony Luck <tipbot@zytor.com> - 2016-10-31 02:30 +0100
  Re: [PATCH v6 00/10] Intel Cache Allocation Technology Thomas Gleixner <tglx@linutronix.de> - 2016-10-31 02:30 +0100
    RE: [PATCH v6 00/10] Intel Cache Allocation Technology "Yu, Fenghua" <fenghua.yu@intel.com> - 2016-10-31 04:10 +0100

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