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Groups > linux.kernel > #1510808
| From | Jiancheng Xue <xuejiancheng@hisilicon.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [RESEND PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC |
| Date | 2016-10-28 03:30 +0200 |
| Message-ID | <sx49C-1i3-83@gated-at.bofh.it> (permalink) |
| References | <suxhL-7bH-9@gated-at.bofh.it> <swUad-3cE-13@gated-at.bofh.it> <sx3dv-Ji-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
在 2016/10/28 8:25, Stephen Boyd 写道: > On 10/27, Rob Herring wrote: >> On Fri, Oct 21, 2016 at 09:37:10AM +0800, Jiancheng Xue wrote: >>> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset >>> Generator) module generates clock and reset signals used >>> by other module blocks on SoC. >>> >>> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> >>> --- >>> change log >>> v2: >>> - Fixed compiling error when compiled as a module. >>> - Fixed issues pointed by Stephen Boyd. >>> - Added prefix HISTB for clock index macro definitions. >> >> What Stephen asked for is send this and the Hi3516CV300 series as one >> series since there is a dependency. > > Exactly. Please resend both parts, along with Rob's ack on this > one. I can review it all then and hopefully Rob will be ok with > the other binding change. > I planed to send the Hi3516CV300 patch after this patch is accepted. It's also OK to combine them as one series. I'll resend them. Thanks, Jiancheng
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Re: [RESEND PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC Rob Herring <robh@kernel.org> - 2016-10-27 16:50 +0200
Re: [RESEND PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC Stephen Boyd <sboyd@codeaurora.org> - 2016-10-28 02:30 +0200
Re: [RESEND PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC Jiancheng Xue <xuejiancheng@hisilicon.com> - 2016-10-28 03:30 +0200
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