Re: [PATCH] mfd: lpss: Fix Intel Kaby Lake PCH-H properties

From	Lee Jones <lee.jones@linaro.org>
Newsgroups	linux.kernel
Subject	Re: [PATCH] mfd: lpss: Fix Intel Kaby Lake PCH-H properties
Date	2016-10-26 12:00 +0200
Message-ID	<swta2-1Sm-1@gated-at.bofh.it> (permalink)
References	<smGrU-2Dz-35@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Thu, 29 Sep 2016, Jarkko Nikula wrote:

> There are a few issues on Intel Kaby Lake PCH-H properties added by
> commit a6a576b78e09 ("mfd: lpss: Add Intel Kaby Lake PCH-H PCI IDs"):
> 
> - Input clock of I2C controller on Intel Kaby Lake PCH-H is 120 MHz not
>   133 MHz. This was probably copy-paste error from Intel Broxton I2C
>   properties.
> - There is no default I2C SDA hold time specified which is used when
>   ACPI doesn't provide it. I got information from Windows driver team
>   that Kaby Lake PCH-H can use the same configuration than Intel
>   Sunrisepoint PCH.
> - Common HS-UART properties are not used.
> 
> Fix these by reusing the Sunrisepoint properties on Kaby Lake PCH-H.
> 
> Fixes: a6a576b78e09 ("mfd: lpss: Add Intel Kaby Lake PCH-H PCI IDs")
> Reported-by: Xiang A Wang <xiang.a.wang@intel.com>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
> ---
>  drivers/mfd/intel-lpss-pci.c | 31 +++++++++----------------------
>  1 file changed, 9 insertions(+), 22 deletions(-)

Applied to -fixes with Mika's Ack.

> diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c
> index 3228fd182a99..9ff243970e93 100644
> --- a/drivers/mfd/intel-lpss-pci.c
> +++ b/drivers/mfd/intel-lpss-pci.c
> @@ -123,19 +123,6 @@ static const struct intel_lpss_platform_info apl_i2c_info = {
>  	.properties = apl_i2c_properties,
>  };
>  
> -static const struct intel_lpss_platform_info kbl_info = {
> -	.clk_rate = 120000000,
> -};
> -
> -static const struct intel_lpss_platform_info kbl_uart_info = {
> -	.clk_rate = 120000000,
> -	.clk_con_id = "baudclk",
> -};
> -
> -static const struct intel_lpss_platform_info kbl_i2c_info = {
> -	.clk_rate = 133000000,
> -};
> -
>  static const struct pci_device_id intel_lpss_pci_ids[] = {
>  	/* BXT A-Step */
>  	{ PCI_VDEVICE(INTEL, 0x0aac), (kernel_ulong_t)&bxt_i2c_info },
> @@ -207,15 +194,15 @@ static const struct pci_device_id intel_lpss_pci_ids[] = {
>  	{ PCI_VDEVICE(INTEL, 0xa161), (kernel_ulong_t)&spt_i2c_info },
>  	{ PCI_VDEVICE(INTEL, 0xa166), (kernel_ulong_t)&spt_uart_info },
>  	/* KBL-H */
> -	{ PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&kbl_uart_info },
> -	{ PCI_VDEVICE(INTEL, 0xa2a8), (kernel_ulong_t)&kbl_uart_info },
> -	{ PCI_VDEVICE(INTEL, 0xa2a9), (kernel_ulong_t)&kbl_info },
> -	{ PCI_VDEVICE(INTEL, 0xa2aa), (kernel_ulong_t)&kbl_info },
> -	{ PCI_VDEVICE(INTEL, 0xa2e0), (kernel_ulong_t)&kbl_i2c_info },
> -	{ PCI_VDEVICE(INTEL, 0xa2e1), (kernel_ulong_t)&kbl_i2c_info },
> -	{ PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&kbl_i2c_info },
> -	{ PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&kbl_i2c_info },
> -	{ PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&kbl_uart_info },
> +	{ PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&spt_uart_info },
> +	{ PCI_VDEVICE(INTEL, 0xa2a8), (kernel_ulong_t)&spt_uart_info },
> +	{ PCI_VDEVICE(INTEL, 0xa2a9), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0xa2aa), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0xa2e0), (kernel_ulong_t)&spt_i2c_info },
> +	{ PCI_VDEVICE(INTEL, 0xa2e1), (kernel_ulong_t)&spt_i2c_info },
> +	{ PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&spt_i2c_info },
> +	{ PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&spt_i2c_info },
> +	{ PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&spt_uart_info },
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids);

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

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Re: [PATCH] mfd: lpss: Fix Intel Kaby Lake PCH-H properties Lee Jones <lee.jones@linaro.org> - 2016-10-26 12:00 +0200

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