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Groups > linux.kernel > #1510197
| From | Thomas Gleixner <tglx@linutronix.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v7 5/6] x86/cpufeature: Detect CPUID faulting support |
| Date | 2016-10-27 16:10 +0200 |
| Message-ID | <swTxw-2VB-7@gated-at.bofh.it> (permalink) |
| References | <stOul-2wo-7@gated-at.bofh.it> <stOul-2wo-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Tue, 18 Oct 2016, Kyle Huey wrote:
>
> +static bool supports_cpuid_faulting(void)
> +{
> + unsigned int lo, hi;
> +
> + if (rdmsr_safe(MSR_PLATFORM_INFO, &lo, &hi))
> + return false;
> +
> + return lo & PLATINFO_CPUID_FAULT;
> +}
> +
> void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
> {
> u32 max_level;
> @@ -54,4 +64,7 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
> if (regs[cb->reg] & (1 << cb->bit))
> set_cpu_cap(c, cb->feature);
> }
> +
> + if (supports_cpuid_faulting())
> + set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
> }
Instead of specific magic for this feature I'd rather like to see something
like the completely untested patch below. That allows us to add MSR based
features trivially in the future.
Thanks,
tglx
8<------------------------
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -24,11 +24,18 @@ enum cpuid_regs {
CR_EBX
};
+struct msr_bit {
+ u16 feature;
+ u16 msr;
+ u8 bit;
+};
+
void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
{
- u32 max_level;
- u32 regs[4];
const struct cpuid_bit *cb;
+ const struct msr_bit *mb;
+ u32 max_level, regs[4];
+ u64 msrval;
static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 },
@@ -42,6 +49,11 @@ void init_scattered_cpuid_features(struc
{ 0, 0, 0, 0, 0 }
};
+ static const struct msr_bit msr_bits[] = {
+ { X86_FEATURE_CPUID_FAULT, MSR_PLATFORM_INFO, 31 },
+ { 0, 0, 0 }
+ };
+
for (cb = cpuid_bits; cb->feature; cb++) {
/* Verify that the level is valid */
@@ -56,4 +68,12 @@ void init_scattered_cpuid_features(struc
if (regs[cb->reg] & (1 << cb->bit))
set_cpu_cap(c, cb->feature);
}
+
+ for (mb = msr_bits; mb->feature; mb++) {
+ if (rdmsrl_safe(mb->msr, &msrval))
+ continue;
+ if (msrval & (1ULL << mb->bit))
+ set_cpu_cap(c, mb->feature);
+ }
+
}
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[PATCH v7 0/6] x86/arch_prctl Add ARCH_[GET|SET]_CPUID for controlling the CPUID instruction Kyle Huey <me@kylehuey.com> - 2016-10-19 04:10 +0200
[PATCH v7 5/6] x86/cpufeature: Detect CPUID faulting support Kyle Huey <me@kylehuey.com> - 2016-10-19 04:10 +0200
Re: [PATCH v7 5/6] x86/cpufeature: Detect CPUID faulting support Thomas Gleixner <tglx@linutronix.de> - 2016-10-27 16:10 +0200
[PATCH v7 3/6] x86/arch_prctl: Add do_arch_prctl_common Kyle Huey <me@kylehuey.com> - 2016-10-19 04:10 +0200
[PATCH v7 1/6] x86/arch_prctl/64: Use SYSCALL_DEFINE2 to define sys_arch_prctl Kyle Huey <me@kylehuey.com> - 2016-10-19 04:10 +0200
[PATCH v7 4/6] x86/syscalls/32: Wire up arch_prctl on x86-32 Kyle Huey <me@kylehuey.com> - 2016-10-19 04:10 +0200
[PATCH v7 6/6] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Kyle Huey <me@kylehuey.com> - 2016-10-19 04:10 +0200
Re: [PATCH v7 6/6] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Thomas Gleixner <tglx@linutronix.de> - 2016-10-27 17:10 +0200
Re: [PATCH v7 6/6] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Andy Lutomirski <luto@amacapital.net> - 2016-10-28 00:40 +0200
Re: [PATCH v7 6/6] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Thomas Gleixner <tglx@linutronix.de> - 2016-10-28 00:50 +0200
[PATCH v7 2/6] x86/arch_prctl/64: Rename do_arch_prctl to do_arch_prctl_64 Kyle Huey <me@kylehuey.com> - 2016-10-19 04:10 +0200
Re: [PATCH v7 0/6] x86/arch_prctl Add ARCH_[GET|SET]_CPUID for controlling the CPUID instruction Kyle Huey <me@kylehuey.com> - 2016-10-25 07:40 +0200
Re: [PATCH v7 0/6] x86/arch_prctl Add ARCH_[GET|SET]_CPUID for controlling the CPUID instruction Thomas Gleixner <tglx@linutronix.de> - 2016-10-25 19:00 +0200
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