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Groups > linux.kernel > #1502434
| From | "Luck, Tony" <tony.luck@intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID |
| Date | 2016-10-17 22:30 +0200 |
| Message-ID | <stmHM-8sQ-11@gated-at.bofh.it> (permalink) |
| References | (1 earlier) <ssjVD-7Za-17@gated-at.bofh.it> <stgsG-47u-15@gated-at.bofh.it> <sthI6-55T-21@gated-at.bofh.it> <stj7c-5TV-37@gated-at.bofh.it> <stjgR-5Xu-13@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Mon, Oct 17, 2016 at 09:43:41AM -0700, Yu, Fenghua wrote:
> > > > I wonder whether this is the proper abstraction level. We might as
> > > > well do the following:
> > > >
> > > > rdtresources[] = {
> > > > {
> > > > .name = "L3",
> > > > },
> > > > {
> > > > .name = "L3Data",
> > > > },
> > > > {
> > > > .name = "L3Code",
> > > > },
> > > >
> > > > and enable either L3 or L3Data+L3Code. Not sure if that makes things
> > > > simpler, but it's definitely worth a thought or two.
> > >
> > > This way will be better than having cdp_enabled/capable for L3 and not
> > > for L2. And this doesn't change current userinterface design either,
> > > I think.
> >
> > User interface would change if you did this. The schemata file would look like
> > this with CDP enabled:
> >
> > # cat schemata
> > L3Data:0=fffff;1=fffff;2=fffff;3=fffff
> > L3Code:0=fffff;1=fffff;2=fffff;3=fffff
> >
> > but that is easier to read than the current:
> >
> > # cat schemata
> > L3:0=fffff,fffff;1=fffff,fffff;2=fffff,fffff;3=fffff,fffff
> >
> > which gives you no clue on which mask is code and which is data.
>
> Right.
>
> Also changing to uniform format <resname>:<id1>=cbm1;<id2>=cbm2;...
> is lot easier to parse schemata line in CDP mode.
>
> So I'll change the code and doc to have two new resources: L3Data and L3Code for CDP mode.
Doc change (fold into part 05):
diff --git a/Documentation/x86/intel_rdt_ui.txt b/Documentation/x86/intel_rdt_ui.txt
index e56781952f42..b9f634c9a058 100644
--- a/Documentation/x86/intel_rdt_ui.txt
+++ b/Documentation/x86/intel_rdt_ui.txt
@@ -97,13 +97,18 @@ With CDP disabled the L3 schemata format is:
L3 details (CDP enabled via mount option to resctrl)
----------------------------------------------------
-When CDP is enabled, you need to specify separate cache bit masks for
-code and data access. The generic format is:
+When CDP is enabled L3 control is split into two separate resources
+so you can specify independent masks for code and data like this:
- L3:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...
+ L3data:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
+ L3code:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
-where the d_cbm masks are for data access, and the i_cbm masks for code.
+L2 details
+----------
+L2 cache does not support code and data prioritization, so the
+schemata format is always:
+ L2:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
Example 1
---------
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[PATCH v4 00/18] Intel Cache Allocation Technology "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
[PATCH v4 02/18] cacheinfo: Introduce cache id "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 02/18] cacheinfo: Introduce cache id Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 12:40 +0200
[PATCH v4 16/18] x86/intel_rdt: Add schemata file "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 16/18] x86/intel_rdt: Add schemata file Thomas Gleixner <tglx@linutronix.de> - 2016-10-18 00:40 +0200
[PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 23:20 +0200
Re: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system "Luck, Tony" <tony.luck@intel.com> - 2016-10-18 00:00 +0200
Re: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system Thomas Gleixner <tglx@linutronix.de> - 2016-10-18 01:00 +0200
RE: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system Thomas Gleixner <tglx@linutronix.de> - 2016-10-18 01:10 +0200
RE: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system "Luck, Tony" <tony.luck@intel.com> - 2016-10-18 01:20 +0200
RE: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system Thomas Gleixner <tglx@linutronix.de> - 2016-10-18 01:30 +0200
RE: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system "Luck, Tony" <tony.luck@intel.com> - 2016-10-18 01:10 +0200
Re: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system Fenghua Yu <fenghua.yu@intel.com> - 2016-10-18 00:20 +0200
Re: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system Thomas Gleixner <tglx@linutronix.de> - 2016-10-18 01:30 +0200
Re: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system "Luck, Tony" <tony.luck@intel.com> - 2016-10-18 01:40 +0200
Re: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system Fenghua Yu <fenghua.yu@intel.com> - 2016-10-18 02:00 +0200
Re: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system Thomas Gleixner <tglx@linutronix.de> - 2016-10-18 12:50 +0200
[PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 15:50 +0200
Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Fenghua Yu <fenghua.yu@intel.com> - 2016-10-17 17:10 +0200
Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID "Luck, Tony" <tony.luck@intel.com> - 2016-10-17 18:40 +0200
RE: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID "Yu, Fenghua" <fenghua.yu@intel.com> - 2016-10-17 18:50 +0200
Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID "Luck, Tony" <tony.luck@intel.com> - 2016-10-17 22:30 +0200
Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 19:10 +0200
Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 19:10 +0200
Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 19:10 +0200
Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Fenghua Yu <fenghua.yu@intel.com> - 2016-10-17 20:20 +0200
[PATCH v4 01/18] Documentation, ABI: Add a document entry for cache id "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 01/18] Documentation, ABI: Add a document entry for cache id Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 12:40 +0200
[PATCH v4 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
[PATCH v4 04/18] x86/intel_rdt: Feature discovery "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
[PATCH v4 11/18] x86/intel_rdt: Add basic resctrl filesystem support "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 11/18] x86/intel_rdt: Add basic resctrl filesystem support Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 21:40 +0200
[PATCH v4 05/18] Documentation, x86: Documentation for Intel resource allocation user interface "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
[PATCH v4 17/18] x86/intel_rdt: Add scheduler hook "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
[PATCH v4 14/18] x86/intel_rdt: Add cpus file "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 14/18] x86/intel_rdt: Add cpus file Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 23:40 +0200
[PATCH v4 12/18] x86/intel_rdt: Add "info" files to resctrl file system "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 12/18] x86/intel_rdt: Add "info" files to resctrl file system Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 21:50 +0200
[PATCH v4 15/18] x86/intel_rdt: Add tasks files "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 15/18] x86/intel_rdt: Add tasks files Thomas Gleixner <tglx@linutronix.de> - 2016-10-18 00:10 +0200
Re: [PATCH v4 15/18] x86/intel_rdt: Add tasks files "Luck, Tony" <tony.luck@intel.com> - 2016-10-18 00:20 +0200
[PATCH v4 10/18] x86/intel_rdt: Build structures for each resource based on cache topology "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 16:50 +0200
[PATCH v4 03/18] x86, intel_cacheinfo: Enable cache id in x86 "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 03/18] x86, intel_cacheinfo: Enable cache id in x86 Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 13:00 +0200
[PATCH v4 07/18] x86/intel_rdt: Add Haswell feature discovery "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-15 01:20 +0200
Re: [PATCH v4 07/18] x86/intel_rdt: Add Haswell feature discovery Thomas Gleixner <tglx@linutronix.de> - 2016-10-17 13:10 +0200
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