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Groups > linux.kernel > #1503068
| From | Vinod Koul <vinod.koul@intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v4] dmaengine: omap-dma: add support for pause of non-cyclic transfers |
| Date | 2016-10-18 16:50 +0200 |
| Message-ID | <stDSi-31t-25@gated-at.bofh.it> (permalink) |
| References | <sqHz4-16x-43@gated-at.bofh.it> <ss2UN-5nz-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Fri, Oct 14, 2016 at 10:30:47AM +0530, Vignesh R wrote: > From: Sebastian Andrzej Siewior <bigeasy@linutronix.de> > > This DMA driver is used by 8250-omap on DRA7-evm. There is one > requirement that is to pause a transfer. This is currently used on the RX > side. It is possible that the UART HW aborted the RX (UART's RX-timeout) > but the DMA controller starts the transfer shortly after. > Before we can manually purge the FIFO we need to pause the transfer, > check how many bytes it already received and terminate the transfer > without it making any progress. > > From testing on the TX side it seems that it is possible that we invoke > pause once the transfer has completed which is indicated by the missing > CCR_ENABLE bit but before the interrupt has been noticed. In that case the > interrupt will come even after disabling it. > > The AM572x manual says that we have to wait for the CCR_RD_ACTIVE & > CCR_WR_ACTIVE bits to be gone before programming it again here is the > drain loop. Also it looks like without the drain the TX-transfer makes > sometimes progress. > > One note: The pause + resume combo is broken because after resume the > the complete transfer will be programmed again. That means the already > transferred bytes (until the pause event) will be sent again. This is > currently not important for my UART user because it does only pause + > terminate. Applied, thanks -- ~Vinod
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[PATCH v4] dmaengine: omap-dma: add support for pause of non-cyclic transfers Vignesh R <vigneshr@ti.com> - 2016-10-14 07:10 +0200 Re: [PATCH v4] dmaengine: omap-dma: add support for pause of non-cyclic transfers Vinod Koul <vinod.koul@intel.com> - 2016-10-18 16:50 +0200
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