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Groups > linux.kernel > #1498012
| From | Robert Jarzmik <robert.jarzmik@free.fr> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 3/3] net: smsc91x: add u16 workaround for pxa platforms |
| Date | 2016-10-09 22:40 +0200 |
| Message-ID | <sqt33-q2-7@gated-at.bofh.it> (permalink) |
| References | <sqt33-q2-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Add a workaround for mainstone, idp and stargate2 boards, for u16 writes
which must be aligned on 32 bits addresses.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Jeremy Linton <jeremy.linton@arm.com>
---
Since v1: rename dt property to pxa-u16-align4
change the binding documentation file
---
Documentation/devicetree/bindings/net/smsc-lan91c111.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
index e77e167593db..309e37eb7c7c 100644
--- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
+++ b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
@@ -13,3 +13,5 @@ Optional properties:
16-bit access only.
- power-gpios: GPIO to control the PWRDWN pin
- reset-gpios: GPIO to control the RESET pin
+- pxa-u16-align4 : Boolean, put in place the workaround the force all
+ u16 writes to be 32 bits aligned
--
2.1.4
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[PATCH v2 1/3] net: smc91x: isolate u16 writes alignment workaround Robert Jarzmik <robert.jarzmik@free.fr> - 2016-10-09 22:40 +0200
[PATCH v2 3/3] net: smsc91x: add u16 workaround for pxa platforms Robert Jarzmik <robert.jarzmik@free.fr> - 2016-10-09 22:40 +0200
[PATCH v2 2/3] net: smc91x: take into account half-word workaround Robert Jarzmik <robert.jarzmik@free.fr> - 2016-10-09 22:40 +0200
Re: [PATCH v2 1/3] net: smc91x: isolate u16 writes alignment workaround Andy Shevchenko <andy.shevchenko@gmail.com> - 2016-10-10 00:00 +0200
Re: [PATCH v2 1/3] net: smc91x: isolate u16 writes alignment workaround Robert Jarzmik <robert.jarzmik@free.fr> - 2016-10-10 08:40 +0200
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