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Re: [PATCH 2/9] mtd: spi-nor: add an alternative method to support memory >16MiB

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On Wednesday 05 October 2016 06:23 PM, Cyrille Pitchen wrote:
> Hi Vignesh,
> 
> Le 05/10/2016 à 14:12, Vignesh R a écrit :
>> Hi,
>>
>>
>> On Tuesday 04 October 2016 10:07 PM, Cyrille Pitchen wrote:
>> [...]
>>>  static struct seq_rw_config stfsm_s25fl_write4_configs[] = {
>>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>>> index 5c87b2d99507..423448c1c7a8 100644
>>> --- a/drivers/mtd/spi-nor/spi-nor.c
>>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>>> @@ -75,6 +75,10 @@ struct flash_info {
>>>  					 * bit. Must be used with
>>>  					 * SPI_NOR_HAS_LOCK.
>>>  					 */
>>> +#define SPI_NOR_4B_OPCODES	BIT(10)	/*
>>> +					 * Use dedicated 4byte address op codes
>>> +					 * to support memory size above 128Mib.
>>> +					 */
>>
>>
>> I don't see this flag being added to any flash_info data for any m25p80
>> compatible flashes? Is that part of a separate series?
>>
> 
> Indeed, this flag is not used yet by any entry in the spi_nor_ids[] array.
> At first, I tested this patch with a Macronix mx25l25673g memory.
> This memory shares the very same JEDEC ID as the older mx25l25635e, so
> I added the SPI_NOR_4B_OPCODES flag in the mx25l25635e entry during my test.
> However I didn't commit this change since the actual mx25l25635e memory
> doesn't support The 4-byte address instruction test.
> 
> Also the mx25l25673g provides the optional 4-byte Address Instruction Table,
> as described in the JESD216 rev B specification, so patches 6 and 7 allow
> to use the 4-byte address op codes without setting the SPI_NOR_4B_OPCODES flag.
> 
> Hence the SPI_NOR_4B_OPCODES, will be useful for memories which don't
> provide the JESD216B 4-byte Address Instruction Table but still support
> the associated op code. It will have to be tested for each individual entry
> in the spi_nor_ids[] array, which can be done later.
> 
> Anyway, the 4-byte address op codes introduced by this patch are also used
> by patch 7 (parse SFDP 4-byte Address Instruction Table).

OK, thanks for the explanation!


-- 
Regards
Vignesh

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[PATCH 0/9] mtd: spi-nor: parse SFDP tables to setup (Q)SPI memories Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-10-04 18:40 +0200
  [PATCH 1/9] mtd: spi-nor: improve macronix_quad_enable() Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-10-04 18:40 +0200
  [PATCH 8/9] mtd: spi-nor: add support to Macronix mx66l1g45g Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-10-04 18:40 +0200
  [PATCH 4/9] mtd: spi-nor: remove unused set_quad_mode() function Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-10-04 18:40 +0200
  [PATCH 7/9] mtd: spi-nor: parse SFDP 4-byte Address Instruction Table Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-10-04 18:40 +0200
  [PATCH 5/9] mtd: m25p80: add support of dual and quad spi protocols to all commands Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-10-04 18:40 +0200
  [PATCH 9/9] mtd: spi-nor: add support to SST sst26* QSPI memories Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-10-04 18:40 +0200
  [PATCH 6/9] mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-10-04 18:40 +0200
  [PATCH 2/9] mtd: spi-nor: add an alternative method to support memory >16MiB Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-10-04 18:40 +0200
    Re: [PATCH 2/9] mtd: spi-nor: add an alternative method to support  memory >16MiB Vignesh R <vigneshr@ti.com> - 2016-10-05 14:20 +0200
      Re: [PATCH 2/9] mtd: spi-nor: add an alternative method to support  memory >16MiB Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-10-05 15:00 +0200
        Re: [PATCH 2/9] mtd: spi-nor: add an alternative method to support  memory >16MiB Vignesh R <vigneshr@ti.com> - 2016-10-06 12:10 +0200
  [PATCH 3/9] mtd: spi-nor: add support of SPI protocols like SPI 1-2-2 and SPI 1-4-4 Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-10-04 18:40 +0200

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