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Re: [PATCH v5 4/9] x86: Enable Intel Turbo Boost Max Technology 3.0

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On Sat, 1 Oct 2016, Srinivas Pandruvada wrote:
> +void sched_set_itmt_support(bool itmt_supported)
> +{
> +	mutex_lock(&itmt_update_mutex);
> +
> +	if (itmt_supported != sched_itmt_capable)
> +		sched_itmt_capable = itmt_supported;

Yikes. What is this conditional for? The only value it has is to confuse
the reader.

> +
> +	mutex_unlock(&itmt_update_mutex);
> +}
> +
> +DEFINE_PER_CPU_READ_MOSTLY(int, sched_core_priority);

Darn. Do not stick variable definitiions in the middle of the code and
especially not glued to the function w/o a newline in between. Move it to
the top of the file.

> +int arch_asym_cpu_priority(int cpu)
> +{
> +	return per_cpu(sched_core_priority, cpu);
> +}


> +void sched_set_itmt_core_prio(int prio, int core_cpu)
> +{
> +	int cpu, i = 1;
> +
> +	for_each_cpu(cpu, topology_sibling_cpumask(core_cpu)) {
> +		int smt_prio;
> +
> +		/*
> +		 * Ensure that the siblings are moved to the end
> +		 * of the priority chain and only used when
> +		 * all other high priority cpus are out of capacity.
> +		 */
> +		smt_prio = prio * smp_num_siblings / i;
> +		i++;

Your code ordering is really random. What has this i++ to do with the
store? Nothing. It just makes reading the code harder. Just move it below
the store.

> +		per_cpu(sched_core_priority, cpu) = smt_prio;

Thanks,

	tglx

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[PATCH v5 0/9] Support Intel® Turbo Boost Max Technology 3.0 Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-10-01 13:50 +0200
  [PATCH v5 8/9] acpi: bus: Set _OSC for diverse core support Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-10-01 13:50 +0200
  [PATCH v5 3/9] x86/topology: Define x86's arch_update_cpu_topology Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-10-01 13:50 +0200
  [PATCH v5 4/9] x86: Enable Intel Turbo Boost Max Technology 3.0 Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-10-01 13:50 +0200
    Re: [PATCH v5 4/9] x86: Enable Intel Turbo Boost Max Technology  3.0 Thomas Gleixner <tglx@linutronix.de> - 2016-10-05 16:30 +0200
      Re: [PATCH v5 4/9] x86: Enable Intel Turbo Boost Max Technology 3.0 Tim Chen <tim.c.chen@linux.intel.com> - 2016-10-05 18:10 +0200
  [PATCH v5 6/9] x86/sched: Add SD_ASYM_PACKING flags to x86 ITMT CPU Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-10-01 13:50 +0200
  [PATCH v5 2/9] x86/topology: Provide topology_num_packages() Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-10-01 13:50 +0200
  [PATCH v5 1/9] sched: Extend scheduler's asym packing Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-10-01 13:50 +0200
    Re: [PATCH v5 1/9] sched: Extend scheduler's asym packing Nilay Vaish <nilayvaish@gmail.com> - 2016-10-01 18:40 +0200
      Re: [PATCH v5 1/9] sched: Extend scheduler's asym packing Tim Chen <tim.c.chen@linux.intel.com> - 2016-10-03 18:50 +0200

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