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Groups > linux.kernel > #1486671
| From | John Keeping <john@metanate.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 19/27] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured |
| Date | 2016-09-19 19:20 +0200 |
| Message-ID | <sjaox-8hd-13@gated-at.bofh.it> (permalink) |
| References | <sjaox-8hd-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Signed-off-by: John Keeping <john@metanate.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 65c89367d8b2..61cee02e5f72 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -414,12 +414,12 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin)); - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div)); dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) | LOW_PROGRAM_EN); dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) | HIGH_PROGRAM_EN); + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); -- 2.10.0.278.g4f427b1.dirty
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[PATCH 19/27] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured John Keeping <john@metanate.com> - 2016-09-19 19:20 +0200
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