Re: [PATCH v2 09/33] x86/intel_rdt: Add L3 cache capacity bitmask management

From	Nilay Vaish <nilayvaish@gmail.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH v2 09/33] x86/intel_rdt: Add L3 cache capacity bitmask management
Date	2016-09-12 18:20 +0200
Message-ID	<sgC7D-5D9-5@gated-at.bofh.it> (permalink)
References	<sf1tv-2mB-5@gated-at.bofh.it> <sf1Dc-2F3-41@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On 8 September 2016 at 04:57, Fenghua Yu <fenghua.yu@intel.com> wrote:
> diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
> index b25940a..9cf3a7d 100644
> --- a/arch/x86/kernel/cpu/intel_rdt.c
> +++ b/arch/x86/kernel/cpu/intel_rdt.c
> @@ -31,8 +31,22 @@ static struct clos_cbm_table *cctable;
>   * closid availability bit map.
>   */
>  unsigned long *closmap;
> +/*
> + * Mask of CPUs for writing CBM values. We only need one CPU per-socket.

Does the second line make sense here?

> + */
> +static cpumask_t rdt_cpumask;
> +/*
> + * Temporary cpumask used during hot cpu notificaiton handling. The usage
> + * is serialized by hot cpu locks.

s/notificaiton/notification


--
Nilay

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Re: [PATCH v2 09/33] x86/intel_rdt: Add L3 cache capacity bitmask management Nilay Vaish <nilayvaish@gmail.com> - 2016-09-12 18:20 +0200

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