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Groups > linux.kernel > #1479979

[PATCH v4 1/9] arm64: Set the safe value for L1 icache policy

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Right now we use 0 as the safe value for CTR_EL0:L1Ip, which is
not defined at the moment. The safer value for the L1Ip should be
the weakest of the policies, which happens to be AIVIVT. While at it,
fix the comment about safe_val.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 arch/arm64/include/asm/cpufeature.h | 2 +-
 arch/arm64/kernel/cpufeature.c      | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index c07c5d1..df47969 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -63,7 +63,7 @@ struct arm64_ftr_bits {
 	enum ftr_type	type;
 	u8		shift;
 	u8		width;
-	s64		safe_val; /* safe value for discrete features */
+	s64		safe_val; /* safe value for FTR_EXACT features */
 };
 
 /*
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index c3d7ae4..4a19138d 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -147,9 +147,10 @@ static const struct arm64_ftr_bits ftr_ctr[] = {
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),	/* DminLine */
 	/*
 	 * Linux can handle differing I-cache policies. Userspace JITs will
-	 * make use of *minLine
+	 * make use of *minLine.
+	 * If we have differing I-cache policies, report it as the weakest - AIVIVT.
 	 */
-	ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),	/* L1Ip */
+	ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_AIVIVT),	/* L1Ip */
 	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),	/* RAZ */
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),	/* IminLine */
 	ARM64_FTR_END,
-- 
2.7.4

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[PATCH v4 0/9] arm64: Work around for mismatched cache line size Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-09 15:10 +0200
  [PATCH v4 7/9] arm64: Introduce raw_{d,i}cache_line_size Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-09 15:10 +0200
  [PATCH v4 4/9] arm64: alternative: Disallow patching instructions using literals Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-09 15:10 +0200
  [PATCH v4 6/9] arm64: alternative: Add support for patching adrp instructions Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-09 15:10 +0200
  [PATCH v4 1/9] arm64: Set the safe value for L1 icache policy Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-09 15:10 +0200
  [PATCH v4 8/9] arm64: Refactor sysinstr exception handling Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-09 15:10 +0200
  [PATCH v4 2/9] arm64: Use consistent naming for errata handling Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-09 15:10 +0200
  [PATCH v4 9/9] arm64: Work around systems with mismatched cache line sizes Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-09 15:10 +0200
  [PATCH v4 3/9] arm64: Rearrange CPU errata workaround checks Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-09 15:10 +0200
  [PATCH v4 5/9] arm64: insn: Add helpers for adrp offsets Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-09 15:10 +0200

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