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Groups > linux.kernel > #1476907
| From | Stefan Agner <stefan@agner.ch> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider |
| Date | 2016-09-05 21:30 +0200 |
| Message-ID | <se7KF-83d-7@gated-at.bofh.it> (permalink) |
| References | <sd20G-3rR-15@gated-at.bofh.it> <se7KF-83d-9@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 2016-09-05 01:46, Meng Yi wrote:
>> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
>>
>> Since using clk_register_divider to setup the pixel clock, regmap is no longer
>> used. Regmap did take care of DCU using different endianness. Check
>> endianness using the device-tree property "big-endian" to determine the
>> location of DIV_RATIO.
>>
>> Cc: stable@vger.kernel.org
>> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
>> clock divider")
>> Reported-by: Meng Yi <meng.yi@nxp.com>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
<snip>
>
> Tested-by: Meng Yi <meng.yi@nxp.com>
> On LS1021A-TWR board.
Thanks, applied!
--
Stefan
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[PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider Stefan Agner <stefan@agner.ch> - 2016-09-02 21:10 +0200 RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider Stefan Agner <stefan@agner.ch> - 2016-09-05 21:30 +0200 RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider Meng Yi <meng.yi@nxp.com> - 2016-09-05 23:30 +0200
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