Re: [PATCH 1/3] perf/x86/intel/bts: Fix confused ordering of PMU callbacks

From	Alexander Shishkin <alexander.shishkin@linux.intel.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH 1/3] perf/x86/intel/bts: Fix confused ordering of PMU callbacks
Date	2016-08-29 16:50 +0200
Message-ID	<sbw2S-62-27@gated-at.bofh.it> (permalink)
References	<s9fIR-1yv-11@gated-at.bofh.it> <s9fIR-1yv-23@gated-at.bofh.it> <s9FtE-2aP-27@gated-at.bofh.it> <s9Hc5-3pN-11@gated-at.bofh.it> <sbvzP-8mr-1@gated-at.bofh.it>
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Peter Zijlstra <peterz@infradead.org> writes:

> On Wed, Aug 24, 2016 at 05:15:54PM +0300, Alexander Shishkin wrote:
>> @@ -221,10 +245,13 @@ static void __bts_event_start(struct perf_event *event)
>>  
>>  	/*
>>  	 * local barrier to make sure that ds configuration made it
>> -	 * before we enable BTS
>> +	 * before we enable BTS and bts::state goes ACTIVE
>>  	 */
>>  	wmb();
>>  
>> +	/* INACTIVE/STOPPED -> ACTIVE */
>> +	WRITE_ONCE(bts->state, BTS_STATE_ACTIVE);
>> +
>>  	intel_pmu_enable_bts(config);
>>  
>>  }
>
> Alexander, were you going to post a new version of this patch without
> the barrier confusion?

Yes, only the testcase exploded again over the weekend, looking at it
again.

Regards,
--
Alex

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Re: [PATCH 1/3] perf/x86/intel/bts: Fix confused ordering of PMU  callbacks Peter Zijlstra <peterz@infradead.org> - 2016-08-29 16:20 +0200
  Re: [PATCH 1/3] perf/x86/intel/bts: Fix confused ordering of PMU callbacks Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2016-08-29 16:50 +0200

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