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Groups > linux.kernel > #1471593
| From | Shawn Guo <shawnguo@kernel.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH] ARM: imx: add cpuidle support for i.mx6ul |
| Date | 2016-08-29 09:30 +0200 |
| Message-ID | <sbpb3-4lM-3@gated-at.bofh.it> (permalink) |
| References | <s9Cm5-8m-3@gated-at.bofh.it> <s9Cm5-8m-1@gated-at.bofh.it> <s9Di9-MJ-5@gated-at.bofh.it> <s9Di9-MJ-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Wed, Aug 24, 2016 at 12:04:50PM +0200, Lucas Stach wrote: > Personally I would just remove the condition, but if you are concerned > about the double L1 flush overhead (I wouldn't worry about this, it > should be negligible) you should really make this conditional on an > architected L2 being present. Making it conditional on the outer cache > being absent is confusing. Anson, Is there any concern or problem if we follow Lucas' suggestion to unconditionally calls flush_cache_all() here? Shawn
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Re: [PATCH] ARM: imx: add cpuidle support for i.mx6ul Shawn Guo <shawnguo@kernel.org> - 2016-08-29 09:30 +0200 RE: [PATCH] ARM: imx: add cpuidle support for i.mx6ul Yongcai Huang <anson.huang@nxp.com> - 2016-08-29 12:10 +0200
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