Re: [PATCH] irqchip/gicv3-its: Enable cacheable attribute Read-allocate hints

From	Marc Zyngier <marc.zyngier@arm.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH] irqchip/gicv3-its: Enable cacheable attribute Read-allocate hints
Date	2016-08-30 10:50 +0200
Message-ID	<sbMU2-2tK-11@gated-at.bofh.it> (permalink)
References	<rTWIa-7PI-3@gated-at.bofh.it> <rU0Vs-2it-11@gated-at.bofh.it> <rU64O-5xF-25@gated-at.bofh.it> <sbwPf-BA-3@gated-at.bofh.it>
Organization	ARM Ltd

Show all headers | View raw

On 29/08/16 16:35, Shanker Donthineni wrote:
> Marc,
> 
> Are you planning to push this change? I talked to Qualcomm ITS hw team 
> and they told me nice to have this change even though we see a small gain.

Hi Shanker,

As I asked before, I'd like to know what is the actual gain on real HW,
and how you measured it, so that I can try and make sure this doesn't
introduce regressions on other implementations. If it does, then we'll
probably have to quirk it.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Back to linux.kernel | Previous | Next — Previous in thread | Find similar | Unroll thread

Thread

Re: [PATCH] irqchip/gicv3-its: Enable cacheable attribute  Read-allocate hints Shanker Donthineni <shankerd@codeaurora.org> - 2016-08-29 17:40 +0200
  Re: [PATCH] irqchip/gicv3-its: Enable cacheable attribute  Read-allocate hints Marc Zyngier <marc.zyngier@arm.com> - 2016-08-30 10:50 +0200

csiph-web