Re: [PATCH] arc: perf: Enable generic "cache-references" and "cache-misses" events

From	Vineet Gupta <Vineet.Gupta1@synopsys.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH] arc: perf: Enable generic "cache-references" and "cache-misses" events
Date	2016-08-26 19:50 +0200
Message-ID	<satqp-1GW-25@gated-at.bofh.it> (permalink)
References	<sa1u9-tW-3@gated-at.bofh.it>
Organization	linux.* mail to news gateway

Show all headers | View raw

On 08/25/2016 04:49 AM, Alexey Brodkin wrote:
> ...
>  	[PERF_COUNT_ARC_EDTLB] = "edtlb",	/* D-TLB Miss */
>  	[PERF_COUNT_ARC_EITLB] = "eitlb",	/* I-TLB Miss */
> +
> +	[PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc",	/* Instr: mem read cached */
> +	[PERF_COUNT_HW_CACHE_MISSES] = "dclm",		/* D-cache Load Miss */

I think this is duplicating a mistake we already have. I vaguely remember when
doing some hackbench profiling last year with range based profiling confined to
memset routine and saw that L1-dcache-misses was counting zero. This is because it
only counts LD misses while memset only does ST.

Performance counter stats for '/sbin/hackbench':

     0 L1-dcache-misses
     0 L1-dcache-load-misses
     1846082 L1-dcache-store-misses

@PeterZ do you concur that is wrong and we ought to setup 2 counters to do this
correctly ?

-Vineet

Thread

[PATCH] arc: perf: Enable generic "cache-references" and "cache-misses" events Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2016-08-25 14:00 +0200
  Re: [PATCH] arc: perf: Enable generic "cache-references" and  "cache-misses" events Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2016-08-26 19:50 +0200
    Re: [PATCH] arc: perf: Enable generic "cache-references" and  "cache-misses" events Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2016-08-31 21:10 +0200
      Re: [PATCH] arc: perf: Enable generic "cache-references" and  "cache-misses" events Peter Zijlstra <peterz@infradead.org> - 2016-09-01 10:40 +0200

csiph-web