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Re: [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips

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On Thu, Dec 29, 2016 at 4:31 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 12/20, Vivek Gautam wrote:
>> PHY transceiver driver for QUSB2 phy controller that provides
>> HighSpeed functionality for DWC3 controller present on
>> Qualcomm chipsets.
>>
>> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
>
> One comment below, but otherwise
>
> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
>
>> +static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
>> +{
>> +     struct device *dev = &qphy->phy->dev;
>> +     u8 *val;
>> +
>> +     /*
>> +      * Read efuse register having TUNE2 parameter's high nibble.
>> +      * If efuse register shows value as 0x0, or if we fail to find
>> +      * a valid efuse register settings, then use default value
>> +      * as 0xB for high nibble that we have already set while
>> +      * configuring phy.
>> +      */
>> +     val = nvmem_cell_read(qphy->cell, NULL);
>> +     if (IS_ERR(val) || !val[0]) {
>> +             dev_dbg(dev, "failed to read a valid hs-tx trim value, %ld\n",
>> +                                                             PTR_ERR(val));
>
> If val is 0 PTR_ERR(0) will be junk? I guess that's ok for debug
> print.

May be -EINVAL is better for debug print. Even when val[0]
is 0, val will still be a valid pointer, and so PTR_ERR(val) will
essentially be the pointer casted to long.



Thanks
Vivek
-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH v3 0/4] phy: USB and PCIe phy drivers for Qcom chipsets Vivek Gautam <vivek.gautam@codeaurora.org> - 2016-12-20 18:20 +0100
  [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips Vivek Gautam <vivek.gautam@codeaurora.org> - 2016-12-20 18:20 +0100
    Re: [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom  chips Stephen Boyd <sboyd@codeaurora.org> - 2016-12-29 00:10 +0100
      Re: [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips Vivek Gautam <vivek.gautam@codeaurora.org> - 2016-12-29 08:00 +0100
        Re: [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips Vivek Gautam <vivek.gautam@codeaurora.org> - 2016-12-29 08:10 +0100
  [PATCH v3 1/4] dt-bindings: phy: Add support for QUSB2 phy Vivek Gautam <vivek.gautam@codeaurora.org> - 2016-12-20 18:20 +0100
    Re: [PATCH v3 1/4] dt-bindings: phy: Add support for QUSB2 phy Rob Herring <robh@kernel.org> - 2016-12-22 22:20 +0100
      Re: [PATCH v3 1/4] dt-bindings: phy: Add support for QUSB2 phy Vivek Gautam <vivek.gautam@codeaurora.org> - 2016-12-23 06:00 +0100
        Re: [PATCH v3 1/4] dt-bindings: phy: Add support for QUSB2 phy Stephen Boyd <sboyd@codeaurora.org> - 2016-12-28 02:20 +0100
          Re: [PATCH v3 1/4] dt-bindings: phy: Add support for QUSB2 phy Vivek Gautam <vivek.gautam@codeaurora.org> - 2016-12-28 06:50 +0100
  Re: [PATCH v3 4/4] phy: qcom-qmp: new qmp phy driver for  qcom-chipsets Stephen Boyd <sboyd@codeaurora.org> - 2016-12-29 00:20 +0100
    Re: [PATCH v3 4/4] phy: qcom-qmp: new qmp phy driver for qcom-chipsets Vivek Gautam <vivek.gautam@codeaurora.org> - 2016-12-29 08:50 +0100

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