[PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

From	Andi Kleen <andi@firstfloor.org>
Newsgroups	linux.kernel
Subject	[PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont
Date	2016-12-03 00:20 +0100
Message-ID	<sK5hv-1NF-5@gated-at.bofh.it> (permalink)
Organization	linux.* mail to news gateway

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From: Andi Kleen <ak@linux.intel.com>

The earlier patch ccbebba4 allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.

Marking for stable because this allows crashing kernels. Also
should be merged for 4.9.

Fixes: ccbebba4 ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
Cc: alexander.shishkin@intel.com
Cc: kan.liang@intel.com
Cc: stable@vger.kernel.org # 4.6+
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 arch/x86/events/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index d0efb5cb1b00..baa1eed55e88 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
 {
 	int i;
 
-	if (x86_pmu.lbr_pt_coexist)
+	if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
 		return 0;
 
 	if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
@@ -387,7 +387,7 @@ fail_unlock:
 
 void x86_del_exclusive(unsigned int what)
 {
-	if (x86_pmu.lbr_pt_coexist)
+	if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
 		return;
 
 	atomic_dec(&x86_pmu.lbr_exclusive[what]);
-- 
2.9.3

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[PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont Andi Kleen <andi@firstfloor.org> - 2016-12-03 00:20 +0100
  Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont Peter Zijlstra <peterz@infradead.org> - 2016-12-06 15:10 +0100
    Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont Andi Kleen <andi@firstfloor.org> - 2016-12-06 16:00 +0100

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