Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]


Groups > linux.kernel > #1530751

[PATCH] arm64: dts: uniphier: add SD-ctrl node for LD11 SoC

From Masahiro Yamada <yamada.masahiro@socionext.com>
Newsgroups linux.kernel
Subject [PATCH] arm64: dts: uniphier: add SD-ctrl node for LD11 SoC
Date 2016-11-26 19:20 +0100
Message-ID <sHPJV-1GL-57@gated-at.bofh.it> (permalink)
Organization linux.* mail to news gateway

Show all headers | View raw


The LD11 SoC is equipped with SD-ctrl (0x59810000) as well as
MIO-ctrl (0x5b3e0000).  The SD-ctrl block on this SoC has just
one register for controlling RST_n pin of the eMMC device.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 0e5c58f..7a62fb9 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -273,6 +273,17 @@
 			reg = <0x59801000 0x400>;
 		};
 
+		sdctrl@59810000 {
+			compatible = "socionext,uniphier-ld11-sdctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x400>;
+
+			sd_rst: reset {
+				compatible = "socionext,uniphier-ld11-sd-reset";
+				#reset-cells = <1>;
+			};
+		};
+
 		perictrl@59820000 {
 			compatible = "socionext,uniphier-perictrl",
 				     "simple-mfd", "syscon";
-- 
2.7.4

Back to linux.kernel | Previous | Next | Find similar | Unroll thread


Thread

[PATCH] arm64: dts: uniphier: add SD-ctrl node for LD11 SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-11-26 19:20 +0100

csiph-web