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[PATCH v3 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K

From Bibby Hsieh <bibby.hsieh@mediatek.com>
Newsgroups linux.kernel
Subject [PATCH v3 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K
Date 2016-08-04 04:50 +0200
Message-ID <s2gTo-2O7-7@gated-at.bofh.it> (permalink)
References <s2gTn-2O7-1@gated-at.bofh.it>
Organization linux.* mail to news gateway

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From: Junzhi Zhao <junzhi.zhao@mediatek.com>

Pixel clock should be 297MHz when resolution is 4K.

Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c |    8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index d05ca79..a90af59 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -438,10 +438,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	}
 
 	pix_rate = 1000UL * mode->clock;
-	if (mode->clock <= 74000)
+	if (mode->clock <= 27000)
+		factor = 16 * 3;
+	else if (mode->clock <= 74250)
 		factor = 8 * 3;
-	else
+	else if (mode->clock <= 167000)
 		factor = 4 * 3;
+	else
+		factor = 2 * 3;
 	pll_rate = pix_rate * factor;
 
 	dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
-- 
1.7.9.5

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Thread

[PATCH v3 0/3] MT8173 HDMI 4K support Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-08-04 04:50 +0200
  [PATCH v3 1/3] drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-08-04 04:50 +0200
  [PATCH v3 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-08-04 04:50 +0200
  [PATCH v3 2/3] drm/mediatek: enhance the HDMI driving current Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-08-04 04:50 +0200

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