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Groups > linux.kernel > #1453440
| From | Brian Norris <briannorris@chromium.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [RESEND PATCH v2 3/8] clk: rockchip: rk3399: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src |
| Date | 2016-08-01 22:20 +0200 |
| Message-ID | <s1rQS-2HG-7@gated-at.bofh.it> (permalink) |
| References | <s1iaS-4Cd-23@gated-at.bofh.it> <s1iaS-4Cd-49@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Mon, Aug 01, 2016 at 05:53:38PM +0800, Xing Zheng wrote:
> There was a typo, swapping 'c' <--> 'g'.
> (This patch is updated and am from https://patchwork.kernel.org/patch/9254067/)
>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> ---
>
> Changes in v2: None
I believe this patch was already applied upstream; otherwise, it
wouldn't make sense to have both this patch and patch 4 -- we would
probably squash them together.
Brian
> drivers/clk/rockchip/clk-rk3399.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index f55f967f..2182391 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -832,9 +832,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
> RK3399_CLKGATE_CON(13), 1, GFLAGS),
>
> /* perihp */
> - GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
> + GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
> RK3399_CLKGATE_CON(5), 0, GFLAGS),
> - GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
> + GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
> RK3399_CLKGATE_CON(5), 1, GFLAGS),
> COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
> RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
> --
> 1.7.9.5
>
>
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[RESEND PATCH v2 0/8] fix and optimize some clock configuration for the RK3399 platfom Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 12:00 +0200
[RESEND PATCH v2 1/8] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 12:00 +0200
[RESEND PATCH v2 3/8] clk: rockchip: rk3399: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 12:00 +0200
Re: [RESEND PATCH v2 3/8] clk: rockchip: rk3399: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src Brian Norris <briannorris@chromium.org> - 2016-08-01 22:20 +0200
Re: [RESEND PATCH v2 3/8] clk: rockchip: rk3399: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src Xing Zheng <zhengxing@rock-chips.com> - 2016-08-02 04:00 +0200
[RESEND PATCH v2 7/8] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 12:20 +0200
[RESEND PATCH v2 5/8] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 12:20 +0200
[RESEND PATCH v2 8/8] clk: rockchip: rk3399: Add support frac mode frequencies Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 12:20 +0200
[RESEND PATCH v2 6/8] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 12:20 +0200
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