Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1453069
| From | Xing Zheng <zhengxing@rock-chips.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 5/7] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI |
| Date | 2016-08-01 11:40 +0200 |
| Message-ID | <s1hRw-4vm-19@gated-at.bofh.it> (permalink) |
| References | <s1hRw-4vm-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 44e673e..580abf1 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
{ /* sentinel */ },
--
1.7.9.5
Back to linux.kernel | Previous | Next | Find similar | Unroll thread
[PATCH v2 5/7] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 11:40 +0200
csiph-web