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Groups > linux.kernel > #1452974
| From | Xing Zheng <zhengxing@rock-chips.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [RESEND PATCH 2/6] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 |
| Date | 2016-08-01 06:30 +0200 |
| Message-ID | <s1d1v-1qO-5@gated-at.bofh.it> (permalink) |
| References | <s1d1v-1qO-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -403,9 +403,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 6, GFLAGS),
- GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
+ GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
- GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
+ GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
--
1.7.9.5
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[RESEND PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 06:30 +0200
[RESEND PATCH 2/6] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 06:30 +0200
[RESEND PATCH 6/6] clk: rockchip: rk3399: Add support frac mode frequencies Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 06:30 +0200
[RESEND PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 06:30 +0200
[RESEND PATCH 4/6] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 06:30 +0200
[RESEND PATCH 5/6] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 06:30 +0200
Re: [RESEND PATCH 5/6] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Shawn Lin <shawn.lin@rock-chips.com> - 2016-08-01 11:10 +0200
[RESEND PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 06:30 +0200
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