Re: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR

From	Andy Gross <andy.gross@linaro.org>
Newsgroups	linux.kernel
Subject	Re: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR
Date	2016-05-12 20:00 +0200
Message-ID	<ry33Z-2al-5@gated-at.bofh.it> (permalink)
References	(1 earlier) <rwSNl-5L9-25@gated-at.bofh.it> <rxEIi-2LV-7@gated-at.bofh.it> <rxGh4-4oy-19@gated-at.bofh.it> <rxRcv-7fp-9@gated-at.bofh.it> <rxS8x-8pY-1@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Thu, May 12, 2016 at 11:48:43AM +0530, Abhishek Sahu wrote:
> On Thu, May 12, 2016 at 12:13:47AM -0500, Andy Gross wrote:
> > On Wed, May 11, 2016 at 11:04:17PM +0530, Abhishek Sahu wrote:
> > 
> > <snip>
> > 
> > > >       In qup_i2c_xfer and qup_i2c_xfer_v2 state is set to RESET at the
> > > >end, when
> > > >       there is no error. So would it be fine if we do it there
> > > >unconditionally ?
> > > >
> > > >Regards,
> > > > Sricharan
> > > 
> > > RESET the QUP state wouldn't create any issue in the case of multiple calls.
> > > The existing code also RESET the QUP state for bus_err but it is not
> > > clearing
> > > status bits.
> > 
> > It'd be better to not reset the QUP inside the ISR at all.  I think the better
> > solution is making the reset occur in the xfer function.  So just clear the bits
> > like you should in the isr, and defer reset till later.
> 
> This is a HW workaround for QUP where we need to RESET the core in
> ISR. When interrupt is level triggerd, more than one interrupt may
> fire in error cases and QUP will generate these interrupts after
> completion of current interrupt. Thus we reset the core immediately
> in the ISR to ward off the next interrupt.

I wonder if that was just an expedient solution.  And it seems like it could be
a little racy as a poll is not being done to make sure the QUP state machine
transitions to reset.  Is there any documentation/errata on this?  Or is this
just from commit comments?


Regards,
Andy

Thread

[PATCH 0/2] i2c: qup: Fixed the DMA transfer errors Abhishek Sahu <absahu@codeaurora.org> - 2016-05-09 14:50 +0200
  [PATCH 1/2] i2c: qup: Cleared the error bits in ISR Abhishek Sahu <absahu@codeaurora.org> - 2016-05-09 14:50 +0200
    RE: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR "Sricharan" <sricharan@codeaurora.org> - 2016-05-11 18:00 +0200
      RE: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR Abhishek Sahu <absahu@codeaurora.org> - 2016-05-11 19:40 +0200
        RE: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR "Sricharan" <sricharan@codeaurora.org> - 2016-05-12 04:30 +0200
        Re: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR Andy Gross <andy.gross@linaro.org> - 2016-05-12 07:20 +0200
          Re: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR Abhishek Sahu <absahu@codeaurora.org> - 2016-05-12 08:20 +0200
            Re: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR Andy Gross <andy.gross@linaro.org> - 2016-05-12 20:00 +0200
              Re: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR Abhishek Sahu <absahu@codeaurora.org> - 2016-05-12 21:40 +0200
                Re: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR Andy Gross <andy.gross@linaro.org> - 2016-05-12 22:10 +0200
                Re: [PATCH 1/2] i2c: qup: Cleared the error bits in ISR Abhishek Sahu <absahu@codeaurora.org> - 2016-05-12 22:30 +0200

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