Re: [PATCH] x86: tsc: Add missing Cherrytrail frequency to the table

From	jeremy.compostella@intel.com (Compostella, Jeremy)
Newsgroups	linux.kernel
Subject	Re: [PATCH] x86: tsc: Add missing Cherrytrail frequency to the table
Date	2016-05-11 17:30 +0200
Message-ID	<rxEfg-2vs-9@gated-at.bofh.it> (permalink)
References	<rxCZP-1jh-1@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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Intel Cherrytrail is based on Airmont core so MSR_FSB_FREQ[2:0] = 4
means that the CPU reference clock runs at 80MHz.  Add this missing
frequency to the table.

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
---
 arch/x86/kernel/tsc_msr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 6aa0f4d..ab271a7 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -23,6 +23,7 @@
 #include <asm/param.h>
 
 /* CPU reference clock frequency: in KHz */
+#define FREQ_80		80000
 #define FREQ_83		83200
 #define FREQ_100	99840
 #define FREQ_133	133200
@@ -56,6 +57,9 @@ static struct freq_desc freq_desc_tables[] = {
 	{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
 	/* ANN */
 	{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
+	/* AIRMONT */
+	{ 6, 0x4c, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, FREQ_80,
+			0, 0, 0 } },
 };
 
 static int match_cpu(u8 family, u8 model)
-- 
1.9.1

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[PATCH] x86: tsc: Add missing Cherrytrail frequency to the table jeremy.compostella@intel.com (Compostella, Jeremy) - 2016-05-11 16:10 +0200
  Re: [PATCH] x86: tsc: Add missing Cherrytrail frequency to the table jeremy.compostella@intel.com (Compostella, Jeremy) - 2016-05-11 17:30 +0200

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