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Re: [PATCH 1/3] dt-bindings: bus: Add documentation for Tegra210 ACONNECT

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On 03/05/16 19:22, Rob Herring wrote:
> On Fri, Apr 29, 2016 at 02:53:45PM +0100, Jon Hunter wrote:
>> Add binding documentation for the Tegra ACONNECT bus that is part of the
>> Audio Processing Engine (APE) on Tegra210. The ACONNECT bus is used to
>> access devices within the APE subsystem. The APE is located in a
>> separate power domain and so accesses made to the ACONNECT require the
>> power domain to be enabled as well as some platform specific clocks.
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>>  .../bindings/bus/nvidia,tegra210-aconnect.txt      | 45 ++++++++++++++++++++++
>>  1 file changed, 45 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt
>>
>> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt
>> new file mode 100644
>> index 000000000000..e5e915f8fca7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt
>> @@ -0,0 +1,45 @@
>> +NVIDIA Tegra ACONNECT Bus
>> +
>> +The Tegra ACONNECT bus is an AXI switch which is used to connnect various
>> +components inside the Audio Processing Engine (APE). All CPU accesses to
>> +the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
>> +
>> +Required properties:
>> +- compatible: Must be "nvidia,tegra210-aconnect".
>> +- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
>> +  and APE interface clock (TEGRA210_CLK_APB2APE).
>> +- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
>> +  'clocks' entries.
>> +- power-domains: Must contain a phandle that points to the audio powergate
>> +  (namely 'aud') for Tegra210.
>> +- #address-cells: The number of cells used to represent physical base addresses
>> +  in the host1x address space. Should be 2.
>> +- #size-cells: The number of cells used to represent the size of an address
>> +  range in the host1x address space. Should be 2.
> 
> Do you really need >4GB of child addresses?

Sounds rather silly when you put it like that. No, its not needed. I
will fix that.

>> +- ranges: 1:1 mapping of the aconnect address space to the CPU address space.
> 
> Why 1:1 for 256KB of address space?

No good reason. I have looking at what we did for host1x and ahub which
also have a ranges property and use a 1:1 mapping. For ahub this makes
sense because it is more of a cross-bar/switch. The aconnect bus is also
a switch and thought may be that is the easiest thing to do. What is
recommended here?

Cheers
Jon

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[PATCH 0/3] bus: Add support for Tegra210 ACONNECT Jon Hunter <jonathanh@nvidia.com> - 2016-04-29 16:00 +0200
  [PATCH 3/3] arm64: tegra: Add ACONNECT bus node for Tegra210 Jon Hunter <jonathanh@nvidia.com> - 2016-04-29 16:00 +0200
  [PATCH 1/3] dt-bindings: bus: Add documentation for Tegra210 ACONNECT Jon Hunter <jonathanh@nvidia.com> - 2016-04-29 16:00 +0200
    Re: [PATCH 1/3] dt-bindings: bus: Add documentation for Tegra210  ACONNECT Rob Herring <robh@kernel.org> - 2016-05-03 20:30 +0200
      Re: [PATCH 1/3] dt-bindings: bus: Add documentation for Tegra210  ACONNECT Jon Hunter <jonathanh@nvidia.com> - 2016-05-05 16:40 +0200
        Re: [PATCH 1/3] dt-bindings: bus: Add documentation for Tegra210 ACONNECT Rob Herring <robh@kernel.org> - 2016-05-05 18:50 +0200
          Re: [PATCH 1/3] dt-bindings: bus: Add documentation for Tegra210  ACONNECT Jon Hunter <jonathanh@nvidia.com> - 2016-05-08 14:50 +0200
  [PATCH 2/3] bus: Add support for Tegra ACONNECT Jon Hunter <jonathanh@nvidia.com> - 2016-04-29 16:00 +0200

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