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[PATCH 05/27] coresight: stm: Bindings for System Trace Macrocell

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The System Trace Macrocell (STM) is an IP block falling under the
CoreSight umbrella.  It's main purpose it so expose stimulus channels
to any system component for the purpose of information logging.

Bindings for this IP block adds a couple of items to the current
mandatory definition for CoreSight components.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
---
 .../devicetree/bindings/arm/coresight.txt          | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 62938eb9697f..93147c0c8a0e 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -19,6 +19,7 @@ its hardware characteristcs.
 		- "arm,coresight-etm3x", "arm,primecell";
 		- "arm,coresight-etm4x", "arm,primecell";
 		- "qcom,coresight-replicator1x", "arm,primecell";
+		- "arm,coresight-stm", "arm,primecell"; [1]
 
 	* reg: physical base address and length of the register
 	  set(s) of the component.
@@ -36,6 +37,14 @@ its hardware characteristcs.
 	  layout using the generic DT graph presentation found in
 	  "bindings/graph.txt".
 
+* Additional required properties for System Trace Macrocells (STM):
+	* reg: along with the physical base address and length of the register
+	  set as described above, another entry is required to describe the
+	  mapping of the extended stimulus port area.
+
+	* reg-names: the only acceptable values are "stm-base" and
+	  "stm-stimulus-base", each corresponding to the areas defined in "reg".
+
 * Required properties for devices that don't show up on the AMBA bus, such as
   non-configurable replicators:
 
@@ -202,3 +211,22 @@ Example:
 			};
 		};
 	};
+
+4. STM
+	stm@20100000 {
+		compatible = "arm,coresight-stm", "arm,primecell";
+		reg = <0 0x20100000 0 0x1000>,
+		      <0 0x28000000 0 0x180000>;
+		reg-names = "stm-base", "stm-stimulus-base";
+
+		clocks = <&soc_smc50mhz>;
+		clock-names = "apb_pclk";
+		port {
+			stm_out_port: endpoint {
+				remote-endpoint = <&main_funnel_in_port2>;
+			};
+		};
+	};
+
+[1]. There is currently two version of STM: STM32 and STM500.  Both
+have the same HW interface and as such don't need an explicit binding name.
-- 
2.5.0

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[PATCH 00/27] coresight: next v4.6-rc6  Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-05-03 19:40 +0200
  [PATCH 26/27] coresight: configuring ETF in FIFO mode when acting as link Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-05-03 19:40 +0200
  [PATCH 14/27] coresight: tmc: introducing new header file Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-05-03 19:40 +0200
  [PATCH 05/27] coresight: stm: Bindings for System Trace Macrocell Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-05-03 19:40 +0200
  [PATCH 04/27] coresight: adding path for STM device Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-05-03 19:50 +0200
  [PATCH 03/27] stm class: Support devices that override software assigned masters Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-05-03 19:50 +0200
  [PATCH 07/27] coresight: etb10: fixing the right amount of words to read Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-05-03 19:50 +0200
  [PATCH 06/27] coresight: stm: adding driver for CoreSight STM component Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-05-03 19:50 +0200
  [PATCH 01/27] coresight: no need to do the forced type conversion Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-05-03 19:50 +0200
    Re: [PATCH 01/27] coresight: no need to do the forced type conversion Greg KH <gregkh@linuxfoundation.org> - 2016-05-04 00:00 +0200

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