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Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for AMD processors

From Andy Lutomirski <luto@amacapital.net>
Newsgroups linux.kernel
Subject Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for AMD processors
Date 2016-04-27 16:50 +0200
Message-ID <rsyWS-2P1-23@gated-at.bofh.it> (permalink)
References <rsx4K-1jL-37@gated-at.bofh.it> <rsyNd-2L2-41@gated-at.bofh.it> <rsyNd-2L2-39@gated-at.bofh.it> <rsyWS-2P1-25@gated-at.bofh.it>
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On Wed, Apr 27, 2016 at 7:44 AM, Tom Lendacky <thomas.lendacky@amd.com> wrote:
> On 04/27/2016 09:33 AM, Andy Lutomirski wrote:
>> On Tue, Apr 26, 2016 at 3:56 PM, Tom Lendacky <thomas.lendacky@amd.com> wrote:
>>> For AMD processors that support PAT, set the write-protect cache mode
>>> (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05).
>>
>> What's the purpose of using the WP memory type?
>
> The WP memory type is used for encrypting or decrypting data "in place".
> The use of the WP on the source data will prevent any of the source
> data from being cached.  Refer to section 7.10.8 "Encrypt-in-Place" in
> the AMD64 APM link provided in the cover letter.
>
> This memory type will be used in subsequent patches for this purpose.

OK.

Why AMD-only?  I thought Intel supported WP, too.

--Andy

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Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for  AMD processors Andy Lutomirski <luto@amacapital.net> - 2016-04-27 16:40 +0200
  Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for  AMD processors Andy Lutomirski <luto@amacapital.net> - 2016-04-27 16:50 +0200
    Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for  AMD processors Andy Lutomirski <luto@amacapital.net> - 2016-04-27 17:20 +0200
      Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for  AMD processors Borislav Petkov <bp@alien8.de> - 2016-04-27 17:40 +0200
        Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for  AMD processors Andy Lutomirski <luto@amacapital.net> - 2016-04-27 17:50 +0200

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