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[PATCH 1/1] perf/x86/intel: Fix wrong lbr_sel_mask

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From: Kan Liang <kan.liang@intel.com>

This patch fixes an issue which starts from 
'commit b16a5b52eb90 ("perf/x86: Add option to disable reading
branch flags/cycles")'. In this patch, lbr_sel_mask is used to mask
the lbr_select. But LBR_SEL_MASK doesn't include the bit for
LBR_CALL_STACK. So LBR call stack will never be set in lbr_select.

This patch corrects the LBR_SEL_MASK by including all valid bits in
LBR_SELECT. Also, the LBR_CALL_STACK bit is different as other bit in
LBR_SELECT. It does not operate in suppress mode, so it needs to be
specially handled in intel_pmu_setup_hw_lbr_filter.

Signed-off-by: Kan Liang <kan.liang@intel.com>
---
 arch/x86/events/intel/lbr.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 317e29e..551d655 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -64,7 +64,7 @@ static enum {
 
 #define LBR_PLM (LBR_KERNEL | LBR_USER)
 
-#define LBR_SEL_MASK	0x1ff	/* valid bits in LBR_SELECT */
+#define LBR_SEL_MASK	0x3ff	/* valid bits in LBR_SELECT */
 #define LBR_NOT_SUPP	-1	/* LBR filter not supported */
 #define LBR_IGN		0	/* ignored */
 
@@ -621,8 +621,10 @@ static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
 	 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
 	 * in suppress mode. So LBR_SELECT should be set to
 	 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
+	 * But the 10th bit LBR_CALL_STACK does not operate
+	 * in suppress mode.
 	 */
-	reg->config = mask ^ x86_pmu.lbr_sel_mask;
+	reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
 
 	if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) &&
 	    (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&
-- 
2.5.0

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[PATCH 1/1] perf/x86/intel: Fix wrong lbr_sel_mask kan.liang@intel.com - 2016-04-21 19:00 +0200
  [tip:perf/core] perf/x86/intel: Fix incorrect lbr_sel_mask value tip-bot for Kan Liang <tipbot@zytor.com> - 2016-04-28 12:30 +0200

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