Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver

From	Stephen Boyd <sboyd@codeaurora.org>
Newsgroups	linux.kernel
Subject	Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver
Date	2016-04-20 04:00 +0200
Message-ID	<rpPAS-8hw-1@gated-at.bofh.it> (permalink)
References	<rmHzQ-4kX-11@gated-at.bofh.it> <rolER-2Dq-3@gated-at.bofh.it> <rpeL0-3XZ-19@gated-at.bofh.it> <rpfQL-4Ut-29@gated-at.bofh.it> <rpzZ8-4qx-1@gated-at.bofh.it>
Organization	linux.* mail to news gateway

Show all headers | View raw

On 04/19, Jose Abreu wrote:
> 
> @Stephen: can you give some input so that I can submit a v6?
> 

I don't prefer putting the second register in the same DT node,
but that's really up to the DT reviewers to approve such a
design. The current binding has been acked by Rob right?

Assuming the new binding is acked/reviewed then that solution is
fine.

Otherwise, I still prefer two DTS files for the two different FPGA
versions. At the least, please use ioremap for any pointers that
you readl/writel here.

Beyond that, we should have a fixed rate source clk somewhere in
the software view of the clk tree, because that reflects reality.
Hardcoding the parent rate in the structure works, but doesn't
properly express the clk tree.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Thread

Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Stephen Boyd <sboyd@codeaurora.org> - 2016-04-16 01:50 +0200
  Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Jose Abreu <Jose.Abreu@synopsys.com> - 2016-04-18 12:40 +0200
    Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2016-04-18 13:50 +0200
      Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Jose Abreu <Jose.Abreu@synopsys.com> - 2016-04-19 11:20 +0200
        Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Stephen Boyd <sboyd@codeaurora.org> - 2016-04-20 04:00 +0200
          Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Jose Abreu <Jose.Abreu@synopsys.com> - 2016-04-20 11:50 +0200
            Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2016-04-20 18:20 +0200
              Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Jose Abreu <Jose.Abreu@synopsys.com> - 2016-04-21 12:00 +0200
                Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2016-04-21 14:20 +0200
                Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Jose Abreu <Jose.Abreu@synopsys.com> - 2016-04-21 15:20 +0200
                Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2016-04-21 16:20 +0200
                Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2016-04-22 08:00 +0200

csiph-web