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Re: [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1

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On 4/12/2016 11:23 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Mon, Mar 21, 2016 at 03:58:52PM -0400, Rhyland Klein wrote:
>> Use a new Tegra210 version of the pll_register_pllre function to
>> allow setting the proper settings for the m and n div fields.
>>
>> Additionally define PLL_RE_OUT1 on Tegra210.
> 
> It'd be nice to specify what that additional clock is used for. No need
> to repost for that, I can add it when applying.
> 

Its not currently directly used on the A44 platform I was testing with,
but from what I understand, it is connected to the Tegra210 debug
interfaces and so its probably good to have it defined in case it is
needed for some debugging.

-rhyland

-- 
nvpublic

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Re: [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1 Thierry Reding <thierry.reding@gmail.com> - 2016-04-12 17:30 +0200
  Re: [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1 Rhyland Klein <rklein@nvidia.com> - 2016-04-15 17:30 +0200

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