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Groups > linux.kernel > #1372181
| From | Andy Lutomirski <luto@amacapital.net> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [REF PATCH] x86/tlb: just do tlb flush on one of siblings of SMT |
| Date | 2016-04-06 06:50 +0200 |
| Message-ID | <rkNzH-6Xf-1@gated-at.bofh.it> (permalink) |
| References | <rkMaB-60f-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Apr 5, 2016 8:17 PM, "Alex Shi" <alex.shi@linaro.org> wrote: > > It seems Intel core still share the TLB pool, flush both of threads' TLB > just cause a extra useless IPI and a extra flush. The extra flush will > flush out TLB again which another thread just introduced. > That's double waste. Do you have a reference in both the SDM and the APM for this? Do we have a guarantee that this serialized the front end such that the non-targetted sibling won't execute an instruction that it decoded from a stale translation? This will conflict rather deeply with my PCID series, too. --Andy
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[REF PATCH] x86/tlb: just do tlb flush on one of siblings of SMT Alex Shi <alex.shi@linaro.org> - 2016-04-06 05:20 +0200
Re: [REF PATCH] x86/tlb: just do tlb flush on one of siblings of SMT Andy Lutomirski <luto@amacapital.net> - 2016-04-06 06:50 +0200
Re: [REF PATCH] x86/tlb: just do tlb flush on one of siblings of SMT Alex Shi <alex.shi@linaro.org> - 2016-04-06 07:20 +0200
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