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Groups > linux.kernel > #1370440
| From | Lars Persson <lars.persson@axis.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v5 2/2] clk: add artpec-6 clock controller |
| Date | 2016-04-04 10:30 +0200 |
| Message-ID | <rk83w-jm-7@gated-at.bofh.it> (permalink) |
| References | <riPcC-uz-15@gated-at.bofh.it> <riPcD-uz-25@gated-at.bofh.it> <rjiHF-4AY-55@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 04/02/2016 03:39 AM, Stephen Boyd wrote:
> On 03/31, Lars Persson wrote:
>> diff --git a/drivers/clk/axis/Makefile b/drivers/clk/axis/Makefile
>> new file mode 100644
>> index 0000000..628c9d3
>> --- /dev/null
>> +++ b/drivers/clk/axis/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
>> diff --git a/drivers/clk/axis/clk-artpec6.c b/drivers/clk/axis/clk-artpec6.c
>> new file mode 100644
>> index 0000000..cf716f1
>> --- /dev/null
[snip]
>
>> +
>> + /* Read PLL1 factors configured by boot strap pins. */
>> + pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
>> + switch (pll_mode) {
>> + case 0: /* DDR3-2133 mode */
>> + pll_m = 4;
>> + pll_n = 85;
>> + break;
>> + case 1: /* DDR3-1866 mode */
>> + pll_m = 6;
>> + pll_n = 112;
>> + break;
>> + case 2: /* DDR3-1600 mode */
>> + pll_m = 4;
>> + pll_n = 64;
>> + break;
>> + case 3: /* DDR3-1333 mode */
>> + pll_m = 8;
>> + pll_n = 106;
>> + break;
>> + }
>> +
>> + clkdata->clk_table[ARTPEC6_CLK_CPU] =
>> + clk_register_fixed_factor(NULL, "cpu", sys_refclk_name, 0, pll_n,
>> + pll_m);
>> + clkdata->clk_table[ARTPEC6_CLK_CPU_PERIPH] =
>> + clk_register_fixed_factor(NULL, "cpu_periph", "cpu", 0, 1, 2);
>> +
>> + /* EPROBE_DEFER on the apb_clock is not handled in amba devices. */
>
> Shouldn't we fix that then?
Marek Szyprowski recently tried to fix this, but Russel NAKed the change
due to userspace breakage:
https://lkml.org/lkml/2016/2/15/555
>
>> + clkdata->clk_table[ARTPEC6_CLK_UART_PCLK] =
>> + clk_register_fixed_factor(NULL, "uart_pclk", "cpu", 0, 1, 8);
>> + clkdata->clk_table[ARTPEC6_CLK_UART_REFCLK] =
>> + clk_register_fixed_rate(NULL, "uart_ref", sys_refclk_name, 0,
>> + 50000000);
>
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[PATCH v5 0/2] clk: Add Artpec-6 SoC support Lars Persson <lars.persson@axis.com> - 2016-03-31 20:10 +0200
[PATCH v5 2/2] clk: add artpec-6 clock controller Lars Persson <lars.persson@axis.com> - 2016-03-31 20:10 +0200
Re: [PATCH v5 2/2] clk: add artpec-6 clock controller Stephen Boyd <sboyd@codeaurora.org> - 2016-04-02 03:40 +0200
Re: [PATCH v5 2/2] clk: add artpec-6 clock controller Lars Persson <lars.persson@axis.com> - 2016-04-04 10:30 +0200
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