Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1369186

[PATCH v4 0/6] Add pinctrl support for Baytrail

Show all headers | View raw

Add support for pin control (pin muxing and pin configuration) for Baytrail
platform.

It follows the design in pinctrl-intel.c, but could not use the
implementation in pinctrl-intel since there were significant differences:
	- gpio pin pads are not ordered
	- per group functions: for setting a certain mode, there are groups
	that need setting pins with different values; for instance, for
	setting USB ULPI pins to GPIO function, pin 2 (GPIO_SUS1) needs
	to be set to function 1, wihle all other from the group need to be
	set to 0
	- communities only need pin base and count as specific data
	- irq set type only clears all flags, while the actual type setting
	is made in the byt_irq_unmask function, which does not comply with
	the intel pinctrl implementation

Changes from v3:
	- fix GPIO_* pin names to match naming conventions used in other
	Intel pinctrl drivers

Changes from v2:
	- remove comment for each enumerated pin
	- apply pin naming conventions used in other Intel drivers

Changes from v1:
	- fix reg, reg_val and byt_soc_data not used variables warnings

Cristina Ciocan (6):
  pinctrl: baytrail: Add pin control data structures
  pinctrl: baytrail: Add pin control operations
  pinctrl: baytrail: Update gpio chip operations
  pinctrl: baytrail: Update irq chip operations
  pinctrl: baytrail: Register pin control handling
  pinctrl: baytrail: Add debounce configuration

 drivers/pinctrl/intel/Kconfig            |    3 +
 drivers/pinctrl/intel/pinctrl-baytrail.c | 1690 +++++++++++++++++++++++++-----
 2 files changed, 1444 insertions(+), 249 deletions(-)

--
1.9.1

Back to linux.kernel | Previous | Next — Next in thread | Find similar | Unroll thread

Thread

[PATCH v4 0/6] Add pinctrl support for Baytrail Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200
  [PATCH 4/7] pinctrl: baytrail: Update gpio chip operations Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200
  [PATCH v4 1/6] pinctrl: baytrail: Add pin control data structures Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200
  [PATCH 3/7] pinctrl: baytrail: Add pin control operations Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200
  [PATCH 5/7] pinctrl: baytrail: Update irq chip operations Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200
  Re: [PATCH v4 0/6] Add pinctrl support for Baytrail Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200
  [PATCH v4 4/6] pinctrl: baytrail: Update irq chip operations Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200
  [PATCH 7/7] pinctrl: baytrail: Add debounce configuration Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200
  [PATCH 2/7] pinctrl: baytrail: Add pin control data structures Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200
  [PATCH v4 3/6] pinctrl: baytrail: Update gpio chip operations Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200
  [PATCH v4 5/6] pinctrl: baytrail: Register pin control handling Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200
  [PATCH v4 2/6] pinctrl: baytrail: Add pin control operations Cristina Ciocan <cristina.ciocan@intel.com> - 2016-04-01 13:00 +0200

csiph-web