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[PATCH 2/9] x86 tsc_msr: Remove debugging messages

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From: Len Brown <len.brown@intel.com>

Debugging messages are not necessary after all of the
possible hardware failures that never occur.
Instead, this code can simply return 0.

This code also doesn't need to print in the success case.
tsc_init() already prints the TSC frequency,
and apic=debug is available if anybody really is
interested in printing the LAPIC frequency.

Signed-off-by: Len Brown <len.brown@intel.com>
---
 arch/x86/kernel/tsc_msr.c | 19 +++----------------
 1 file changed, 3 insertions(+), 16 deletions(-)

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index c16e35b..d460ef1 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -76,9 +76,10 @@ static int match_cpu(u8 family, u8 model)
 	(freq_desc_tables[cpu_index].freqs[freq_id])
 
 /*
- * Do MSR calibration only for known/supported CPUs.
+ * MSR-based CPU/TSC frequency discovery for certain CPUs.
  *
- * Returns the calibration value or 0 if MSR calibration failed.
+ * Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy
+ * Return processor base frequency in KHz, or 0 on failure.
  */
 unsigned long try_msr_calibrate_tsc(void)
 {
@@ -100,31 +101,17 @@ unsigned long try_msr_calibrate_tsc(void)
 		rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
 		ratio = (hi >> 8) & 0x1f;
 	}
-	pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
-
-	if (!ratio)
-		goto fail;
 
 	/* Get FSB FREQ ID */
 	rdmsr(MSR_FSB_FREQ, lo, hi);
 	freq_id = lo & 0x7;
 	freq = id_to_freq(cpu_index, freq_id);
-	pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
-				freq_id, freq);
-	if (!freq)
-		goto fail;
 
 	/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
 	res = freq * ratio;
-	pr_info("TSC runs at %lu KHz\n", res);
 
 #ifdef CONFIG_X86_LOCAL_APIC
 	lapic_timer_frequency = (freq * 1000) / HZ;
-	pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
 #endif
 	return res;
-
-fail:
-	pr_warn("Fast TSC calibration using MSR failed\n");
-	return 0;
 }
-- 
2.8.0.rc4.16.g56331f8

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[PATCH 0/9] x86: TSC calibration update Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200
  [PATCH 6/9] x86 tsc_msr: Extend to include Intel Core Architecture Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200
  [PATCH 2/9] x86 tsc_msr: Remove debugging messages Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200
  [PATCH 9/9] x86 tsc: enumerate BXT tsc_khz via CPUID Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200
  [PATCH 4/9] x86 tsc_msr: Correct Silvermont reference clock values Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200
  [PATCH 5/9] x86 tsc_msr: Add Airmont reference clock values Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200

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