Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1367802

[PATCH 6/9] x86 tsc_msr: Extend to include Intel Core Architecture

Show key headers only | View raw

From: Len Brown <len.brown@intel.com>

tsc_msr is used to quickly and reliably
enumerate the CPU/TSC frequencies at boot time
For the Intel Atom Architecture.

Extend tsc_msr to include recent Intel Core Architecture.

As this code discovers BCLK, it also sets lapic_timer_frequency,
which allows LAPIC timer calibration to be skipped,
though it is already skipped on systems with a TSC deadline timer.

Signed-off-by: Len Brown <len.brown@intel.com>
---
 arch/x86/kernel/tsc_msr.c | 49 +++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 41 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 59c371e..c8ea977 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -77,23 +77,56 @@ unsigned long try_msr_calibrate_tsc(void)
 	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
 		return 0;
 
+	/*
+	 * 100 MHz BCLK Core Architecture -- before SKL.
+	 * De-rate 100Mhz by about 0.25% to account
+	 * for the average effect of spread-spectrum clocking.
+	 */
+	switch (boot_cpu_data.x86_model) {
+
+	case 0x2A:	/* SNB */
+	case 0x3A:	/* IVB */
+		freq = 99773;
+		goto get_ratio;
+	case 0x2D:	/* SNB Xeon */
+	case 0x3E:	/* IVB Xeon */
+		freq = 99760;
+		goto get_ratio;
+	case 0x3C:	/* HSW */
+	case 0x3F:	/* HSW */
+	case 0x45:	/* HSW */
+	case 0x46:	/* HSW */
+	case 0x3D:	/* BDW */
+	case 0x47:	/* BDW */
+	case 0x4F:	/* BDX */
+	case 0x56:	/* BDX-DE */
+		freq = 99769;
+		goto get_ratio;
+	}
+
+	/*
+	 * Atom Architecture
+	 */
 	cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
 	if (cpu_index < 0)
 		return 0;
 
-	if (freq_desc_tables[cpu_index].msr_plat) {
-		rdmsr(MSR_PLATFORM_INFO, lo, hi);
-		ratio = (lo >> 8) & 0x1f;
-	} else {
-		rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
-		ratio = (hi >> 8) & 0x1f;
-	}
-
 	/* Get FSB FREQ ID */
 	rdmsr(MSR_FSB_FREQ, lo, hi);
 	freq_id = lo & 0x7;
 	freq = id_to_freq(cpu_index, freq_id);
 
+	if (!freq_desc_tables[cpu_index].msr_plat) {
+		rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+		ratio = (hi >> 8) & 0x1f;
+		goto done;
+	}
+
+get_ratio:
+	rdmsr(MSR_PLATFORM_INFO, lo, hi);
+	ratio = (lo >> 8) & 0x1f;
+
+done:
 	/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
 	res = freq * ratio;
 
-- 
2.8.0.rc4.16.g56331f8

Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread

Thread

[PATCH 0/9] x86: TSC calibration update Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200
  [PATCH 6/9] x86 tsc_msr: Extend to include Intel Core Architecture Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200
  [PATCH 2/9] x86 tsc_msr: Remove debugging messages Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200
  [PATCH 9/9] x86 tsc: enumerate BXT tsc_khz via CPUID Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200
  [PATCH 4/9] x86 tsc_msr: Correct Silvermont reference clock values Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200
  [PATCH 5/9] x86 tsc_msr: Add Airmont reference clock values Len Brown <lenb@kernel.org> - 2016-03-31 06:20 +0200

csiph-web