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Groups > linux.kernel > #1366020
| From | tip-bot for Peter Zijlstra <tipbot@zytor.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [tip:x86/urgent] perf/x86/amd: Cleanup Fam10h NB event constraints |
| Date | 2016-03-29 11:00 +0200 |
| Message-ID | <rhXFg-3uj-3@gated-at.bofh.it> (permalink) |
| References | <reKXU-6YK-9@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Commit-ID: 32b62f446827f696cc474a6d83cea93693c5ed49
Gitweb: http://git.kernel.org/tip/32b62f446827f696cc474a6d83cea93693c5ed49
Author: Peter Zijlstra <peterz@infradead.org>
AuthorDate: Fri, 25 Mar 2016 15:52:35 +0100
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Tue, 29 Mar 2016 10:45:04 +0200
perf/x86/amd: Cleanup Fam10h NB event constraints
Avoid allocating the AMD NB event constraints data structure when not
needed. This gets rid of x86_max_cores usage and avoids allocating
this on AMD Core Perfctr supporting hardware (which has separate MSRs
for NB events).
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: aherrmann@suse.com
Cc: Rui Huang <ray.huang@amd.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: jencce.kernel@gmail.com
Link: http://lkml.kernel.org/r/20160320124629.GY6375@twins.programming.kicks-ass.net
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/events/amd/core.c | 21 ++++++++++++++++++---
arch/x86/events/perf_event.h | 5 +++++
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 049ada8d..86a9bec 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -369,7 +369,7 @@ static int amd_pmu_cpu_prepare(int cpu)
WARN_ON_ONCE(cpuc->amd_nb);
- if (boot_cpu_data.x86_max_cores < 2)
+ if (!x86_pmu.amd_nb_constraints)
return NOTIFY_OK;
cpuc->amd_nb = amd_alloc_nb(cpu);
@@ -388,7 +388,7 @@ static void amd_pmu_cpu_starting(int cpu)
cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
- if (boot_cpu_data.x86_max_cores < 2)
+ if (!x86_pmu.amd_nb_constraints)
return;
nb_id = amd_get_nb_id(cpu);
@@ -414,7 +414,7 @@ static void amd_pmu_cpu_dead(int cpu)
{
struct cpu_hw_events *cpuhw;
- if (boot_cpu_data.x86_max_cores < 2)
+ if (!x86_pmu.amd_nb_constraints)
return;
cpuhw = &per_cpu(cpu_hw_events, cpu);
@@ -648,6 +648,8 @@ static __initconst const struct x86_pmu amd_pmu = {
.cpu_prepare = amd_pmu_cpu_prepare,
.cpu_starting = amd_pmu_cpu_starting,
.cpu_dead = amd_pmu_cpu_dead,
+
+ .amd_nb_constraints = 1,
};
static int __init amd_core_pmu_init(void)
@@ -674,6 +676,11 @@ static int __init amd_core_pmu_init(void)
x86_pmu.eventsel = MSR_F15H_PERF_CTL;
x86_pmu.perfctr = MSR_F15H_PERF_CTR;
x86_pmu.num_counters = AMD64_NUM_COUNTERS_CORE;
+ /*
+ * AMD Core perfctr has separate MSRs for the NB events, see
+ * the amd/uncore.c driver.
+ */
+ x86_pmu.amd_nb_constraints = 0;
pr_cont("core perfctr, ");
return 0;
@@ -693,6 +700,14 @@ __init int amd_pmu_init(void)
if (ret)
return ret;
+ if (num_possible_cpus() == 1) {
+ /*
+ * No point in allocating data structures to serialize
+ * against other CPUs, when there is only the one CPU.
+ */
+ x86_pmu.amd_nb_constraints = 0;
+ }
+
/* Events are common for all AMDs */
memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index ba6ef18..716d048 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -608,6 +608,11 @@ struct x86_pmu {
atomic_t lbr_exclusive[x86_lbr_exclusive_max];
/*
+ * AMD bits
+ */
+ unsigned int amd_nb_constraints : 1;
+
+ /*
* Extra registers for events
*/
struct extra_reg *extra_regs;
Back to linux.kernel | Previous | Next — Previous in thread | Find similar | Unroll thread
[PATCH 2/3] x86/topology: Fix AMD core count Peter Zijlstra <peterz@infradead.org> - 2016-03-18 16:10 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Borislav Petkov <bp@alien8.de> - 2016-03-18 17:50 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Borislav Petkov <bp@alien8.de> - 2016-03-21 09:30 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Borislav Petkov <bp@alien8.de> - 2016-03-21 09:30 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Borislav Petkov <bp@alien8.de> - 2016-03-21 11:30 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Peter Zijlstra <peterz@infradead.org> - 2016-03-21 09:30 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Borislav Petkov <bp@alien8.de> - 2016-03-21 15:00 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Borislav Petkov <bp@alien8.de> - 2016-03-22 12:30 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Thomas Gleixner <tglx@linutronix.de> - 2016-03-21 10:00 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Thomas Gleixner <tglx@linutronix.de> - 2016-03-19 10:30 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Borislav Petkov <bp@alien8.de> - 2016-03-19 17:00 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Peter Zijlstra <peterz@infradead.org> - 2016-03-20 11:50 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Borislav Petkov <bp@alien8.de> - 2016-03-20 12:10 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Peter Zijlstra <peterz@infradead.org> - 2016-03-20 13:40 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Peter Zijlstra <peterz@infradead.org> - 2016-03-20 13:50 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Borislav Petkov <bp@alien8.de> - 2016-03-20 14:10 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Peter Zijlstra <peterz@infradead.org> - 2016-03-20 18:20 +0100
Re: [PATCH 2/3] x86/topology: Fix AMD core count Borislav Petkov <bp@alien8.de> - 2016-03-20 19:50 +0100
[tip:x86/urgent] perf/x86/amd: Cleanup Fam10h NB event constraints tip-bot for Peter Zijlstra <tipbot@zytor.com> - 2016-03-29 11:00 +0200
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