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[PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed

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On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPLL,
there is incorrect to select bit_0 and bit_1 as the main and alternate
parents for LPLL/BPLL. They should be configurable.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

Changes in v5: None
Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-cpu.c |   15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 5556849..4bb130c 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -258,7 +258,7 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
 		return ERR_PTR(-ENOMEM);
 
 	init.name = name;
-	init.parent_names = &parent_names[0];
+	init.parent_names = &parent_names[reg_data->mux_core_main];
 	init.num_parents = 1;
 	init.ops = &rockchip_cpuclk_ops;
 
@@ -276,10 +276,10 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
 	cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
 	cpuclk->hw.init = &init;
 
-	cpuclk->alt_parent = __clk_lookup(parent_names[1]);
+	cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);
 	if (!cpuclk->alt_parent) {
-		pr_err("%s: could not lookup alternate parent\n",
-		       __func__);
+		pr_err("%s: could not lookup alternate parent: (%d)\n",
+		       __func__, reg_data->mux_core_alt);
 		ret = -EINVAL;
 		goto free_cpuclk;
 	}
@@ -291,10 +291,11 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
 		goto free_cpuclk;
 	}
 
-	clk = __clk_lookup(parent_names[0]);
+	clk = __clk_lookup(parent_names[reg_data->mux_core_main]);
 	if (!clk) {
-		pr_err("%s: could not lookup parent clock %s\n",
-		       __func__, parent_names[0]);
+		pr_err("%s: could not lookup parent clock: (%d) %s\n",
+		       __func__, reg_data->mux_core_main,
+		       parent_names[reg_data->mux_core_main]);
 		ret = -EINVAL;
 		goto free_alt_parent;
 	}
-- 
1.7.9.5

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Thread

[PATCH v5 0/4] Add more clock compatible features and support the RK3399 clock Xing Zheng <zhengxing@rock-chips.com> - 2016-03-26 07:40 +0100
  [PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed Xing Zheng <zhengxing@rock-chips.com> - 2016-03-26 07:40 +0100
    Re: [PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed Heiko Stübner <heiko@sntech.de> - 2016-03-27 23:30 +0200
  [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller Xing Zheng <zhengxing@rock-chips.com> - 2016-03-26 07:40 +0100
    Re: [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller Heiko Stübner <heiko@sntech.de> - 2016-03-28 02:00 +0200
      Re: [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller Heiko Stuebner <heiko@sntech.de> - 2016-03-28 02:10 +0200
        Re: [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller Xing Zheng <zhengxing@rock-chips.com> - 2016-03-28 05:30 +0200
      Re: [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller Xing Zheng <zhengxing@rock-chips.com> - 2016-03-28 05:00 +0200
  Re: [PATCH v5 4/4] clk: rockchip: add clock controller for the RK3399 Heiko Stuebner <heiko@sntech.de> - 2016-03-28 02:20 +0200
    Re: [PATCH v5 4/4] clk: rockchip: add clock controller for the RK3399 Xing Zheng <zhengxing@rock-chips.com> - 2016-03-28 08:20 +0200

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