[PATCH 05/23] perf list: Fix documentation of :ppp

From	Arnaldo Carvalho de Melo <acme@kernel.org>
Newsgroups	linux.kernel
Subject	[PATCH 05/23] perf list: Fix documentation of :ppp
Date	2016-03-23 22:20 +0100
Message-ID	<rfYm6-S2-17@gated-at.bofh.it> (permalink)
References	<rfYm5-S2-3@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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From: Andi Kleen <ak@linux.intel.com>

Correctly document what is implemented for :ppp on Intel CPUs in recent
kernels.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1458575793-12091-2-git-send-email-andi@firstfloor.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/Documentation/perf-list.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt
index 79483f40e991..ec723d0a5bb3 100644
--- a/tools/perf/Documentation/perf-list.txt
+++ b/tools/perf/Documentation/perf-list.txt
@@ -40,10 +40,12 @@ address should be. The 'p' modifier can be specified multiple times:
  0 - SAMPLE_IP can have arbitrary skid
  1 - SAMPLE_IP must have constant skid
  2 - SAMPLE_IP requested to have 0 skid
- 3 - SAMPLE_IP must have 0 skid
+ 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
+     sample shadowing effects.
 
 For Intel systems precise event sampling is implemented with PEBS
-which supports up to precise-level 2.
+which supports up to precise-level 2, and precise level 3 for
+some special cases
 
 On AMD systems it is implemented using IBS (up to precise-level 2).
 The precise modifier works with event types 0x76 (cpu-cycles, CPU
-- 
2.5.5

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[PATCH 05/23] perf list: Fix documentation of :ppp Arnaldo Carvalho de Melo <acme@kernel.org> - 2016-03-23 22:20 +0100

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